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Explanation of FIFO-Mode in SPI (TMS320F28035)

Other Parts Discussed in Thread: TMS320F28035

can someone explain to me the FIFO mode for SPI on the TMS320F28035.

It is currently disabled for me and I can send and receive data. but what is the advantage of a FIFOS and is it advisable to activate it?
thank you for your help

Kind regards


  • Markus,

    The FIFOs will make transmission and reception more efficient if you are sending/receiving many characters at the same time. By more efficient I mean less CPU SPI interrupts or less CPU SPI status polling. The CPU will also have a longer amount of time service the FIFO, which can help if the CPU is loaded with other higher-priority tasks.

    Without FIFO

    - TX: Load a character, wait for it to transmit, load another character.

    - RX: Wait for a character, read the character, wait for another character.

    With FIFO

    - TX: Wait for X FIFO spaces to be available, load X characters to FIFO.

    - RX: Wait for Y characters to be received, read Y characters from FIFO.