**Part Number:**C2000WARE-DIGITALPOWER-SDK

Hi team,

Here's an issue from the customer may need your help:

1) In the tidud61e document, the actual current direction is opposite to the reference direction in the grid-tied state, in the positive half, according to the current reference direction of Figure 2-8 which should be negative.

However, according to the zero-terminal Hall connection of the schematic, current enters from the IP- terminal and the output voltage is lower than the hall mid-point bias. In the sub-program for zero-line current sampling, the Hall output voltage minus the midpoint is biased negative and multiplied by -2.0 is positive (per unit), but the actual and reference current direction is reversed. Why's this?

2) In the current loop calculation program, the error is the current feedback minus reference.

Assuming a reference of 0.5 at some point in the positive half cycle, the current sampling is 0.51 and the error is positive 0.01. Through the current regulator, the corresponding output should be increased such that D is larger so that VxiN is higher. The inductor voltage, the loop resistance voltage drop, the AC voltage drop direction is also the current reference direction according to KVL -VIN+VL+VR+VBUS=0. VBUS = VIN-VL-VR, VL=VIN-VBUS-VR.

The positive half-cycle VIN is positive and the negative half-cycle VIN is negative, which matches the plot block to the right of Figure 2-9.

Higher VxiN means a higher Q3 turn-on duty cycle, resulting in a higher grid-tied current (and reverse reference direction), which becomes positive feedback? Could you help elaborate on the whole process and logic?

Thanks a lot.

Best Regards,

Cherry