Other Parts Discussed in Thread: C2000WARE
I have a board which i can program with the XDS110 debugger and runs perfectly well when this is attached. However when run from FLASH without the debugger the board runs normally following a Power on Reset but doesn't run when reset using XRS.
XRS has a 2k2 pull up and 10nF to ground.
TRST has 2k2 pull down.
Z1_BOOTCTRL is set to 0x5E5D0B5A which i think is boot from flash using GPIO 78 and 79 as boot select. 78/79 are normally pulled high. The rest of the OTP is set to 1s.
Interestingly if i pull GPIO78/79 low then it operates correctly from XRS but not from POR - however i think this may be misleading.
While the application code is rather more complicated. I have replicated this with a basic flashing LED example based on the first example in C2000Ware. The relevant extracts are below - minimal changes from the stock. The boot pins and clock have been changed because of board constraints.
It appears that on XRS the PC is at 0x3FEFB3, whereas the start of main is 0x085025 however i do not understand why these two things are different or how to change the entry point of XRS, any help is greatly appreciated. Specifically;
1. Are there different entry points for XRS vs POR and if so how do i set them?
2. Is there anything i've missed in the OTP which i need to set to enable the correct behaviour
What else have i missed?
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_OSC2 | SYSCTL_IMULT(40) | \
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
SYSCTL_PLL_ENABLE)
Main.c
#include "driverlib.h"
#include "device.h"
#define LED1_PIN 66
#define LED1_CFG GPIO_66_GPIO66
#define LED_DIR GPIO_DIR_MODE_OUT
#define LED_TYPE GPIO_PIN_TYPE_STD
//
// Main
//
void main(void)
{
// device Initialisation
Device_init();
//Initialise GPIO and configure the GPIO pin as a push-pull output
Device_initGPIO();
//Initialise PIE and clear PIE registers. Disables CPU interrupts
Interrupt_initModule();
//Initialise the PIE vector table
Interrupt_initVectorTable();
GPIO_setPinConfig(LED1_CFG);
GPIO_setDirectionMode(LED1_PIN, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(LED1_PIN, GPIO_PIN_TYPE_STD);
//Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
EINT;
ERTM;
//Loop forever
while(1)
{
//Turn on LED
GPIO_writePin(LED1_PIN, 0);
//Delay for a bit
DEVICE_DELAY_US(100000);
//Turn off LED
GPIO_writePin(LED1_PIN, 1);
//Delay for a bit
DEVICE_DELAY_US(100000);
}
}
F2837xD_CodeStartBranch.asm
-----------------------------------------------------------------------------------------------------------------------------------------------
***********************************************************************
WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 .ref _c_int00 .global code_start *********************************************************************** * Function: codestart section * * Description: Branch to code starting point *********************************************************************** .sect "codestart" .retain code_start: .if WD_DISABLE == 1 LB wd_disable ;Branch to watchdog disable code .else LB _c_int00 ;Branch to start of boot._asm in RTS library .endif ;end codestart section *********************************************************************** * Function: wd_disable * * Description: Disables the watchdog timer *********************************************************************** .if WD_DISABLE == 1 .text wd_disable: SETC OBJMODE ;Set OBJMODE for 28x object code EALLOW ;Enable EALLOW protected register access MOVZ DP, #7029h>>6 ;Set data page for WDCR register MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD EDIS ;Disable EALLOW protected register access LB _c_int00 ;Branch to start of boot._asm in RTS library .endif ;end wd_disable .end ;// ;// End of file. ;//
2837xS_Generic_FLASH_lnk.cmd
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000123, length = 0x0002DD
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
/* BANK 1 */
FLASHO : origin = 0x0C0000, length = 0x002000 /* on-chip Flash */
FLASHP : origin = 0x0C2000, length = 0x002000 /* on-chip Flash */
FLASHQ : origin = 0x0C4000, length = 0x002000 /* on-chip Flash */
FLASHR : origin = 0x0C6000, length = 0x002000 /* on-chip Flash */
FLASHS : origin = 0x0C8000, length = 0x008000 /* on-chip Flash */
FLASHT : origin = 0x0D0000, length = 0x008000 /* on-chip Flash */
FLASHU : origin = 0x0D8000, length = 0x008000 /* on-chip Flash */
FLASHV : origin = 0x0E0000, length = 0x008000 /* on-chip Flash */
FLASHW : origin = 0x0E8000, length = 0x008000 /* on-chip Flash */
FLASHX : origin = 0x0F0000, length = 0x008000 /* on-chip Flash */
FLASHY : origin = 0x0F8000, length = 0x002000 /* on-chip Flash */
FLASHZ : origin = 0x0FA000, length = 0x002000 /* on-chip Flash */
FLASHAA : origin = 0x0FC000, length = 0x002000 /* on-chip Flash */
FLASHBB : origin = 0x0FE000, length = 0x001FF0 /* on-chip Flash */
// FLASHBB_RSVD : origin = 0x0FFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x000FF8
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(8)
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
codestart : > BEGIN PAGE = 0, ALIGN(8)
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
#if defined(__TI_EABI__)
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS3, PAGE = 0
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS5, PAGE = 1
.sysmem : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASHF, PAGE = 0, ALIGN(8)
#else
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
.cio : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHF PAGE = 0, ALIGN(8)
#endif
/* Initalized sections go in Flash */
.switch : > FLASHB PAGE = 0, ALIGN(8)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#endif
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
/* The following section definitions are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
