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TMS320F28377D-Q1: Bypass Capacitor of VDDIO-VDDOSC-VDDA

Part Number: TMS320F28377D-Q1
Other Parts Discussed in Thread: TMDSCNCD28379D, LAUNCHXL-F28379D, C2000WARE

Dear Sir,

As I am designing hardware of TMS320F28377, I want to consult on the Bypass circuit design of VDDx.

Usually in my experience I will using via for bypassing the pin by putting the capacitor directly bottom of microcontroller as picture

This design will ensure that capacitor will be closest to VDDx pin and save a lot of space (already pass though inductance/ferrite bead nearby)

Anyway, as I follow the TI LAUNCHXL board  design, I found that they are using many Inductance for each VDDIO, VDDOSC, VDDA separately.

Why ?  and If it really ncessary ?

Because it will add a lot of hardware design constanit to PCB board, which may resulting in not able to use all-pins available / instead PCB layer&cost.

I would like to confirm that if I use all VDDIO-VDDOSC-VDDA domain as VDD_MCU(3.3VDC) with passing though 30ohm ferrite bead will be fesiable ?

Would it have any hardware impact of stability design ?

Best regards,
Narudol T. 

  • This design will ensure that capacitor will be closest to VDDx pin

    While I agree this is a good way to do place these I feel its prudent to say that this is not the closest layout to the pin, you are ignoring the 62mils added by going though the Via.

    Why ?  and If it really ncessary ?

    These are ferrite beads. The idea is to try and suppress noise from crossing into the different power domains on the device. They are not strictly required, but again work to suppress noise. If you wish to only use one, that too could be acceptable. It partially depends on how much noise you expect in your system.

    I don't think there should be too many restrictions to use these 3 ferrite beads, and I wouldn't expect it to limit the pins able to be brought out. But I do appreciate how device fanout can be difficult when using only a few layers. We provide TMDSCNCD28379D and Launchxl-F28379D as layout references in our C2000ware package.

    Regards,
    Cody 

  • Thank you Cody,

    Yes, I design only 4 layers S1 - POWER - GND - S2 for saving cost.

    Thank you for suggestion of the layout referenece  as well.


    Best regards,

    Narudol T.