TMS320F28069M: Loading INSTASPIN program to FLASH

Pavlin Stoyanoff

Part Number: TMS320F28069M
Other Parts Discussed in Thread: LAUNCHXL-F28069M

Greetings! My project is based on INSTASPIN labs. So I took lab1b and added my code. So now I want to load this program to the FLASH memory of the controller. My board is based on LAUNCHXL-F28069M. So I have 2.2kohms pull down on TRST, TDO and GPIO34. 910ohm pull ups after the swith on TDO and GPIO34. My GPIO34 pin is configured as general purpuse input. I think I have the necessary code in my project:

extern uint16_t *RamfuncsLoadStart, *RamfuncsLoadEnd, *RamfuncsRunStart;

#ifdef CSM_ENABLE
extern uint16_t *econst_start, *econst_end, *econst_ram_load;
extern uint16_t *switch_start, *switch_end, *switch_ram_load;
#endif
#endif

void System_Init()
{
    #ifdef FAST_ROM_V1p6
      uint_least8_t ctrlNumber = 1;
    #endif

      // Only used if running from FLASH
      // Note that the variable FLASH is defined by the project
      #ifdef FLASH
      // Copy time critical code and Flash setup code to RAM
      // The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
      // symbols are created by the linker. Refer to the linker files.
      memCopy((uint16_t *)&RamfuncsLoadStart,(uint16_t *)&RamfuncsLoadEnd,(uint16_t *)&RamfuncsRunStart);

      #ifdef CSM_ENABLE
        //copy .econst to unsecure RAM
        if(*econst_end - *econst_start)
          {
            memCopy((uint16_t *)&econst_start,(uint16_t *)&econst_end,(uint16_t *)&econst_ram_load);
          }

        //copy .switch ot unsecure RAM
        if(*switch_end - *switch_start)
          {
            memCopy((uint16_t *)&switch_start,(uint16_t *)&switch_end,(uint16_t *)&switch_ram_load);
          }
      #endif
      #endif
}

The first function I call is this System_init(). I have FLASH defined.I don`t use CSM. I am compiling the program with F28069M.cmd as linker file. I tested several combinations of the switch - TRST connected to the programmer and not, GPIO34 high and low. No effect. There is nothing on the microcontroller. What am I doing wrong? Is it possible the devider on GPIO34 to prevent registering logical "1" on it? The voltage there is below 3V(2.5V i think)? Do i have to configure the GPIO34 in hal.c as a reserved function?

Here is my entire code:

CNCRouter simple program v08 11 2022.rar

Any suggestions?

Thanks!

over 1 year ago

0 Luke Jones over 1 year ago

TI__Genius 10660 points

Hi Pavlin, our linker file expert will be able to answer your question shortly, thank you for your patience.

0 Pavlin Stoyanoff over 1 year ago in reply to Luke Jones

Expert 1465 points

Thanks! I found this theme : Click

I think I have done everything discribed inthere , but still these is no progres. I have FLASH defined in the predifined section. I have memcopy.c, codestartbranch.asm, RAM_link is excluded from compilation and so on. I can execute the program when my xds100v3 is connected to the target, but when I remove it, it doesn`t fire...

In addition I removed the 910ohms pullup resistor on GPIO34 switch pin, so now when I turn on this switch it connects GPIO34 directly to Vcc.

Any other suggestions?

Thanks, again!

0 Veena Kamath over 1 year ago in reply to Pavlin Stoyanoff

TI__Mastermind 31525 points

Hi,

Could you share the linker cmd file you have used? If it is already present in the rar file, could you point me to the location?

Here is an FAQ which might be helpful - https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/878674/faq-flash---how-to-modify-an-application-from-ram-configuration-to-flash-configuration

Regards,

Veena

0 Pavlin Stoyanoff over 1 year ago in reply to Veena Kamath

Expert 1465 points

here is the file ->

/*
//###########################################################################
//
// FILE:    F28069.cmd
//
// TITLE:   Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: F2806x C/C++ Header Files and Peripheral Examples V135 $ 
// $Release Date: Sep 8, 2012 $ 
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i). */
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0_1     : origin = 0x008000, length = 0x000C00     /* on-chip RAM block L0 and L1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA_B    : origin = 0x3F0000, length = 0x007F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	 /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDC30, length = 0x000B50    /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE780, length = 0x00008C    /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE80C, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2_3     : origin = 0x008C00, length = 0x001400     /* on-chip RAM block L2 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x001800     /* on-chip RAM block L8. From 0x13800 to 0x14000 is reserved for InstaSPIN */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA_B,   PAGE = 0
   .pinit              : > FLASHA_B,   PAGE = 0
   .text               : > FLASHA_B,   PAGE = 0
   codestart           : > BEGIN,      PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0_1,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0,      PAGE = 1
   .ebss               : > RAML2_3,    PAGE = 1
   .esysmem            : > RAML2_3,    PAGE = 1

   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA_B,   PAGE = 0
   .switch             : > FLASHA_B,   PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA_B,   PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML5	           : > RAML5,      PAGE = 1
   DMARAML6	           : > RAML6,      PAGE = 1
   DMARAML7	           : > RAML7,      PAGE = 1
   DMARAML8	           : > RAML8,      PAGE = 1   

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables3
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.  */
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

THis is F28069M.cmd. I can`t upload it in some reason. Sorry I have forgotten it in the zip file, because i use a separate laptop for embedded developing. It is a high voltage device and I don`t want to use my main computer.

0 Veena Kamath over 1 year ago in reply to Pavlin Stoyanoff

TI__Mastermind 31525 points

Also, are you facing the issue while programming the .out or while running? Can you give some details on the error you are facing

Regards,

Veena

0 Pavlin Stoyanoff over 1 year ago in reply to Veena Kamath

Expert 1465 points

I can execute the project on the controller, but it doesn`t work on its own. When I load the project to the uC it runs, but when I power cycle the uC, nothing happnes...

I added the csi interrupt to ramfuncs - no luck. Is it possible that my flash definitions are not in the main.c, but in system.c to cause this problem?

0 Veena Kamath over 1 year ago in reply to Pavlin Stoyanoff

TI__Mastermind 31525 points

Can you check the FAQ I shared earlier? There is a section on common issues found while running standalone

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/878674/faq-flash---how-to-modify-an-application-from-ram-configuration-to-flash-configuration

Regards,

Veena

0 Pavlin Stoyanoff over 1 year ago in reply to Veena Kamath

Expert 1465 points

OK! I will return feedback soon!

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TMS320F28069M: Loading INSTASPIN program to FLASH