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TMS320F28069: SCI will lose data when sending them under FIFO interruption mode

Part Number: TMS320F28069

Hi Team,

I sent the interruption code:

To be compatible with 2 SCI ports, the sciNo set a variable listed as follows:

#define SCI_FIFO_CHAR_NUM 1

	if (SCI_TX_Len_Remained[sciNo] >= SCI_FIFO_CHAR_NUM)
	{
		while (i < SCI_FIFO_CHAR_NUM)
		{
			sciRegs->SCITXBUF = SCI_TX_Buffer[sciNo][SCI_TX_Index[sciNo] + i++];
		}
		SCI_TX_Len_Remained[sciNo] -= SCI_FIFO_CHAR_NUM;
		SCI_TX_Index[sciNo] += SCI_FIFO_CHAR_NUM;
		//Set the TxFIFO interruption
	}
	//The rest of data to be sent is less than 4 bytes
	else if (SCI_TX_Len_Remained[sciNo] > 0)
	{
		while (i < SCI_TX_Len_Remained[sciNo])
		{
			sciRegs->SCITXBUF = SCI_TX_Buffer[sciNo][SCI_TX_Index[sciNo] + i++];
		}
		SCI_TX_Len_Remained[sciNo] = 0;
		SCI_TX_Index[sciNo] = 0;
	}
	//There are no data left to be sent
	else
	{
	    /** Disable the FIFO sending interruption. Otherwise, it will always be interrupted and end up here*/
	    sciRegs->SCIFFTX.bit.TXFFIENA = 0;
		/** The sending of the last byte hasn't been finished. A symbol has been placed*/
		if(!sciRegs->SCICTL2.bit.TXEMPTY)
			SCI_Wait_LastChar[sciNo] = 1;
	}

Part of the code regarding SCI’s initialization:

	sciRegs->SCICTL1.bit.TXENA = 1;
	sciRegs->SCICTL1.bit.RXENA = 1;

	sciRegs->SCICTL2.bit.TXINTENA = 0;
	sciRegs->SCICTL2.bit.RXBKINTENA = 0;

	/** Set Baud rate */
	Uint16 brr = SCI_ConvertBAUD(baud);
	sciRegs->SCIHBAUD = (brr >> 8) & 0xFF;
	sciRegs->SCILBAUD = (brr & 0xFF);

	sciRegs->SCIFFTX.all = 0xC000;
	sciRegs->SCIFFRX.all = 0x0024;
	sciRegs->SCIFFCT.all = 0x000B;

	/** The soft reset of SCI*/
	sciRegs->SCICTL1.all = 0x0063;
	sciRegs->SCIFFTX.bit.TXFIFORESET = 1; // Re-enable rx FIFO operation
	sciRegs->SCIFFRX.bit.RXFIFORESET = 1; // Re-enable tx FIFO operation

The actual test found (character loss means that the receiver should have received N characters, but it only received N minus X characters, and X would vary with configuration changes):

  1. When “SCI_FIFO_CHAR_NUM <= 4”, the data could be sent smoothly. Otherwise, some characters in the data being sent would be lost.
  2. When I set TCFFIL to 16 and SCI_FIFO_CHAR_NUM to 16, more characters in the data being sent would be lost.
  3. When I entered the TXFFINT interruption, if I wrote (16 minus TXFFST) bytes continuously into SCITXBUF, a large number of characters in the data being sent would also be lost.

My query is:

Since the condition to trigger TXFFINT after TXFFIENA is enabled is “TXFFST <= TXFFIL”, when TXFFINT enters interruption, can I continue to write (16 minus TXFFST) bytes in the FIFO in this case?

The original intention of using FIFO is to reduce the number of interruption so as to reduce the CPU load, but the desired effect cannot be obtained.

Kind regards,

Katherine

  • Hi Katherine,

    Since the condition to trigger TXFFINT after TXFFIENA is enabled is “TXFFST <= TXFFIL”, when TXFFINT enters interruption, can I continue to write (16 minus TXFFST) bytes in the FIFO in this case?

    You could, I think the best implementation would be to write to the tx buffer once TXFFST indicates the FIFO is empty (to save you CPU time). 

    Best Regards,

    Marlyn