TMS320F28055: Need Code to read Analog channel B

Hello Sudip,

I looked through the Example_2805xAdcSoc example project and it seems that the B channel is selected using inputs 8-15 in the appropriate registers. Did you try modifying this project to use that?

Best regards,

Omer Amir

Hi  Omer Amir,

Thank you so much for your prompt response.

The example is :Example_2805xAdcSoc.c

Actually, i need to  read all ADC IN B  channel input one by one.  which register settings for INA/INB selection?

can you please provide exapme code?

Best Regards-

sudip

EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.ADCINT1 = &adc_isr;
EDIS; // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize all the Device Peripherals:
//
InitAdc(); // For this example, init the ADC
AdcOffsetSelfCal();

//
// Step 5. User specific code, enable __interrupts:
//
// Enable ADCINT1 in PIE
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
IER |= M_INT1; // Enable CPU Interrupt 1
EINT; // Enable Global __interrupt INTM
ERTM; // Enable Global realtime __interrupt DBGM

LoopCount = 0;
ConversionCount = 0;

//
// Configure ADC
// Notes:
// Channel ADCINA4 will be double sampled to workaround the ADC 1st
// sample issue for rev0 silicon errata.
// Due to round-robin, SOC0 converts first, then SOC1, then SOC2
//
EALLOW;
AdcRegs.ADCCTL1.bit.INTPULSEPOS= 1; //ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; //Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 2; //setup EOC2 to trigger ADCINT1
AdcRegs.ADCSOC0CTL.bit.CHSEL = 4; //set SOC0 channel select to ADCINA4
AdcRegs.ADCSOC1CTL.bit.CHSEL = 4; //set SOC1 channel select to ADCINA4
AdcRegs.ADCSOC2CTL.bit.CHSEL = 2; //set SOC2 channel select to ADCINA2
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //set SOC0 start trigger on EPWM1A
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5; //set SOC1 start trigger on EPWM1A
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 5; //set SOC2 start trigger on EPWM1A
AdcRegs.ADCSOC0CTL.bit.ACQPS = 9; //SOC0 S/H Window = 10 (9+1) Clk Cycles
AdcRegs.ADCSOC1CTL.bit.ACQPS = 9; //SOC0 S/H Window = 10 (9+1) Clk Cycles
AdcRegs.ADCSOC2CTL.bit.ACQPS = 9; //SOC0 S/H Window = 10 (9+1) Clk Cycles
EDIS;

//
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
//
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start

//
// Wait for ADC __interrupt
//
for(;;)
{
LoopCount++;
}
}

__interrupt void adc_isr(void)
{
//
//Discard ADCRESULT0 as part of the workaround to rev0's 1st sample errata
//
Voltage1[ConversionCount] = AdcResult.ADCRESULT1;
Voltage2[ConversionCount] = AdcResult.ADCRESULT2;

//
// If 10 conversions have been logged, start over
//
if(ConversionCount == 9)
{
ConversionCount = 0;
}
else
{
ConversionCount++;
}

//
// Clear ADCINT1 flag reinitialize for next SOC
//
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge __interrupt to PIE

return;
}

 Hi Omer Amir, 

Thank you so much for your valuable reply. May be I am missing something. 

I will retry again.

Best regards-

sudip

Hello Sudip,

SUDIP CHAKRABORTY said:

Actually, i need to  read all ADC IN B  channel input one by one.  which register settings for INA/INB selection?

can you please provide exapme code?

The code here is sufficient for this device, you only need to change the values you are using in the CHSEL and other places to use the B channel, the bitfields used should be the same. If you want to read all the inputs on channel B, you just need to configure all 16 SOCs (you can copy the existing code for configuring the SOCs and just change the SOC number so that you include 0 through 15). You can look at the "ADC SOC0-SOC15 Control Registers (ADCSOCxCTL)" section in the reference manual to get an idea of what you would need to change in the SOC control registers. It's up to you on what triggers you want to use, or if you want to do a software trigger.

Best regards,

Omer Amir

Hi Omer Amir,

Thank you so much for your reply. I did the experiment based on your info. Now I am able to read channel B.

But one issue.

I noticed, B1,B4,B6,B7 not able to read.
rest B channel for +vcc=4095 count, 0V=0 count.
and the said channel +/- same value ~519 count.

Can you please let me know why this issue? the config as below:

Best Regards-
sudip

main()
{
////////////////////////////////////////
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();

////////////////<InitAdc()>///////////////////////////
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
EDIS;

EALLOW;
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power ADC BG
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // Enable ADC
AdcRegs.ADCCTL1.bit.ADCREFSEL = 0; // Select internal BG
EDIS;
DELAY_US(1000);
////////////////////////////////////////////////////////
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
IER |= M_INT1; // Enable CPU Interrupt 1
EINT; // Enable Global __interrupt INTM
ERTM; // Enable Global realtime __interrupt DBGM

EALLOW;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 15; // value 9,12,14,15 no response
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //set SOC0 start trigger on EPWM1A
AdcRegs.ADCSOC0CTL.bit.ACQPS = 9; //SOC0 S/H Window = 10 (9+1) Clk Cycles
EDIS;

//
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start

for(;;)
{
unsigned int r0 = AdcResult.ADCRESULT0;
}
}

Hello Sudip,

I noticed that you don't have the AdcOffsetSelfCal() function which re-calibrates the ADC zero offset error, is there a reason for this? Also can you explain your hardware setup for this? Are you using a ControlCARD?

Best regards,

Omer Amir