CCSTUDIO3: Breakpoints

I have only 3 breakpoints set. The the first 2 lines are:

   104  byteData = SCI_readCharBlockingNonFIFO(SCIA_BASE);

    116 SCI_writeCharNonBlocking(SCIA_BASE,byteData);

Why are they being skipped? There is no flow control.

CCS finally stops on this line:

126 return FLASH_UPDATE_ERROR_SCI_DATA_WORD_KEY;

uint32_t SCI_Boot(uint32_t bootMode)
{
    uint32_t entryAddress;
    uint16_t byteData;

/*
    //
    // CPU1 Patch/Escape Point 13
    //
    entryAddress = CPU1BROM_TI_OTP_ESCAPE_POINT_13;
    if((entryAddress != 0xFFFFFFFFUL) &&
       (entryAddress != 0x00000000UL))
    {
        //
        // If OTP is programmed, then call OTP patch function
        //
        ((void (*)(void))entryAddress)();
    }
*/
    //
    // Check if SCI is enabled on device or not
    //
    //if((HWREG(DEVCFG_BASE + SYSCTL_O_DC8) & SYSCTL_DC8_SCI_A) == 0U)
    if(SysCtl_isPeripheralPresent(SYSCTL_PERIPH_PRESENT_SCIA) != 0x01)
    {
        return(FLASH_UPDATE_ERROR_SCIA_NOT_ENABLED);
    }

    //
    // Assign GetWordData to the SCI-A version of the
    // function. GetWordData is a pointer to a function.
    //
    uint16_t (*GetWordData)(void);
    GetWordData = SCIA_GetWordData;

    //
    // Initialize the SCI-A port for communications
    // with the host.
    //

    //
    // Enable the SCI-A clocks
    //
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA);
    SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4);

    EALLOW;
    HWREGH(SCIA_BASE + SCI_O_FFTX) = SCI_FFTX_SCIRST;

    //
    // 1 stop bit, No parity, 8-bit character
    // No loopback
    //
    HWREGH(SCIA_BASE + SCI_O_CCR) = (SCI_CONFIG_WLEN_8 | SCI_CONFIG_STOP_ONE);
    SCI_setParityMode(SCIA_BASE,SCI_CONFIG_PAR_NONE);

    //
    // Enable TX, RX, Use internal SCICLK
    //
    HWREGH(SCIA_BASE + SCI_O_CTL1) = (SCI_CTL1_TXENA | SCI_CTL1_RXENA);

    //
    // Disable RxErr, Sleep, TX Wake,
    // Disable Rx Interrupt, Tx Interrupt
    //
    HWREGB(SCIA_BASE + SCI_O_CTL2) = 0x0U;

    //
    // Relinquish SCI-A from reset and enable TX/RX
    //
    SCI_enableModule(SCIA_BASE);

    EDIS;

    //
    // GPIO INIT
    //
    //SCIBOOT_configure_gpio(bootMode);

    //
    // CPU1 Patch/Escape Point 13
    //
    entryAddress = 0;//CPU1BROM_TI_OTP_ESCAPE_POINT_13;
    if((entryAddress != 0xFFFFFFFFUL) &&
       (entryAddress != 0x00000000UL))
    {
        //
        // If OTP is programmed, then call OTP patch function
        //
        ((void (*)(void))entryAddress)();
    }

    //
    // Perform autobaud lock with the host.
    // Note that if autobaud never occurs
    // the program will hang in this routine as there
    // is no timeout mechanism included.
    //
    //SCI_lockAutobaud(SCIA_BASE);

    //
    // Read data
    //
    byteData = SCI_readCharBlockingNonFIFO(SCIA_BASE);

    //
    // Configure TX pin after autobaud lock
    // (Performed here to allow SCI to double as wait boot)
    //
    //GPIO_setPadConfig(SCI_gpioTx,GPIO_PIN_TYPE_PULLUP);
    //GPIO_setPinConfig(SCI_gpioTxPinConfig);

    //
    // Write data to request key
    //
    SCI_writeCharNonBlocking(SCIA_BASE,byteData);

    //
    // If the KeyValue was invalid, abort the load
    // and return the flash entry point.
    //
    uint16_t gwd = 0;
    gwd = SCIA_GetWordData();
    if(SCIA_GetWordData() != SCI_DATA_WORD_KEY)
    {
        return FLASH_UPDATE_ERROR_SCI_DATA_WORD_KEY;
    }