TIDM-02000: Question ADC Oversampling

Hi Gokhan,

Gokhan G. said:

1) I read some documents and investigating related software. I see that LV output is sampled differently at different documents. I'm trying the figure out why TI changed ADC reading philisophy.

   At document tidu248 and HVPSFB user guide, there is oversampling at low voltage output. (Year of 2012 and 2014)

    At document TIDM-02000, there is no oversampling at low voltage output. (Year of 2021)

   1.a ) Could you please explain why TI changed ADC sampling topology in years? 

   1.b) There is explanation on benefits of about ADC oversampling at tidu248. Is there any drawback that caused change in years.

Thanks for pointing out this. It is correct to do ADC over-sampling as we did in tidu248 and HVPSFB user guide. TIDM-02000 was used to demonstrate the PCMC PSFB using type-4 pwm at that time. There is no drawback of doing over-sampling in tidu248.

Gokhan G. said:

2) How is the timing of the ADC triggering is generated for ADC oversampling? I understood that 4 samples during counting up, 4 samples during counting down. However, I couldn't understand how the ADC is progrramed?Could you please explain in details? Can you refer to code section?

I believe you can use CMPC/CMPB/PRD/ZERO of PWM module to create the ADC SOC which are averagely spread over single PWM cycle. 

Gokhan G. said:

3) Which function does make the averaging of the result of ADC samples? Can you refer to code section?

You may check the HVPSFB design or tidm-bidir-400-12. With current devices, the averaging part is realized in the s/w in one of the ISR. It is just to add up the sampling points and do a simple averaging.

Regards,

Chen