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TIDM-1000: boardstatus_BuslmbalanceTrip

Part Number: TIDM-1000

Hi team,

Here's an issue from the customer may need your help:

When the kit is loaded at 300 ohms, the input phase voltage is 70 V, and Bulid2 is established, and active rectification is not started. Monitoring the output with CCS is shown in the following figure: 

When active rectification is initiated, an imbalance in the upper and lower capacitor voltage values is detected, causing the protection feature to be triggered:

What could be the possible cause of this issue? Could you help check this case? Thanks.

Best Regards,


  • Hi Cherry,

    First, can you confirm they follow the test procedure in the user guide? is everything ok under build 1?

    Looks like once the current loop is closed, there is significant unbalance for three phase PWM output. You may want to double check the current sensing(though looks fine based on the expression window you attached) and the three phase PWM output?

    Can you also send the PWM output waveform of the second condition(after you clear the flag to close the current loop)?