Other Parts Discussed in Thread: SYSCONFIG, C2000WARE
Hi
I am generating complementary EPWM using the DB module but want to modify EPWM1B before it goes out to the pin. To keep the problem simple to begin with, in the Tile I just ANDed
the input i0 signal (EPWM1B) with a 1. If I set the CLB overriding to Output 2 (EPWM1B) according to the table below all I get is a continuous low coming out on EPWM1B pin when I would expect just a
copy of the original input EPWM1B signal. If I set the overriding to Output 0, EPWM1A pin also goes low, but one sees fine pulses that match the transitions of the EPWM1B. Screenshots attached.
If I assign no overriding output then EPWM1A and 1B appear as "unchanged" PWM as expected on the respective pins.
as
Ultimately I want to use CMPSS1 to modify EPWM1B as reflected in the CLB setup below. This can occur before or after the TZ module as I will just be ANDing the two signals. But I cannot
even get it to go when I ignore i1 which I have assigned to CMPSS1 (AUXSIG0). I copied clb_ex12 on intersecting outputs extensively but cannot see what I am doing wrong.
I would note that I set up EPWM1 and CMPSS1 without using Sysconfig, instead direct using driverlib.
Can someone spot what I might being doing wrong?
Thanks
Andrew