TMS320F28335: When is SW updated value is active on a AQCTLA register ?

Hi Hidehiko-san,

According to our TRM there is a table that shows the priorities depending on your count mode configurations. Doing a software force event will have highest priority and affect the active settings immeditately.

Best,

Ryan Ma

Hi Ryan-san,

Thank you for your information.

Our setting is Up-Down count mode.

And "software force event" is configured with AQSFRC register.

My question is about "AQCTLA" register.

When my software change, are CAU and CAD (bits field)  updated immediately ?

EPwm1Regs.AQCTLA.all= 0x0090U

In other words, when time-base counter is currently counting up, software updates CAD bits field.

It immediately affects the event(CMPA=TBCTR) ?

or it affects the event at the timing (CTR=ZERO) ?

Best regards,

Hidehiko

Hi Hidehiko-San,

I have not been able to test this out on my end. However there is a post regarding the same device and situation you are facing.

According to this user : https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/861218/ccs-tms320f28335-how-to-make-aqctla-take-effect-at-point-c

It happened at TBCTR = ZERO. Could you verify this on your end when testing it? If you can confirm this, it will be great to know.

Best,

Ryan Ma

Hi Ryan-san,

Thank you for your information.

My question is about ePWM submodule design specification

because I have not found description on technical reference manual.

I need detailed design specification about timing to be active.

As you know, ePWM support a shadow  register for CMPA and a user configure a load timing.

However there is no related description about AQCTLA .

Actually static configuration does not need that information

however spraai1.pdf (Using the ePWM Module for 0% - 100% Duty Cycle Control) is provided. AQCTLA.bit.CAU and AQCTLA.bit.CAD are dynamically changed in an interrupt function.

So far on my end, it seems that AQCTLA register is updated immediately.

My implementation avoids to change CAD in count decrementing and CAU in count incrementing

because it is not possible to adjust timing between CMPA=CTR event and CAU/CAD changed.

In count incrementing, CAU=(No change), CAD=(possible change)

In count decrementing, CAU=(possible change), CAD=(No change)

Best regards,

Hidehiko

Hi Hidehiko, 

As you know the shadow registers for counter compare will be updated on a certain event. Since this device does not use shadow registers for the AQCTLA like CMPA, I would assume the update happens immediately. Let me test this on my end to verify though and get back to you with some oscilloscope waveforms.

Best,

Ryan Ma

Hi Hidehiko, 

As you know the shadow registers for counter compare will be updated on a certain event. Since this device does not use shadow registers for the AQCTLA like CMPA, I would assume the update happens immediately. Let me test this on my end to verify though and get back to you with some oscilloscope waveforms.

Here is my findings

ePWM1 output before trip interrupt that changes AQCTLA

• Original settings
• AQCTLA = 0x0060
• 

ePWM1 output after trip interrupt

• Updated with setting output to low on CMPA events
• AQCTLA = 0x0050
• 

Here is my interrupt occuring when GPIO13 get's connected to GND.

__interrupt void 
epwm1_tzint_isr(void)
{
    EPwm1TZIntCount++;

    //
    // Leave these flags set so we only take this
    // interrupt once
    //
    // 	EALLOW;
    // 	EPwm1Regs.TZCLR.bit.OST = 1;
    // 	EPwm1Regs.TZCLR.bit.INT = 1;
    //	EDIS;
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;             // Set PWM1A on CAU
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;           // Clear PWM1A on CAD
    //
    // Acknowledge this interrupt to receive more interrupts from group 2
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
}

It looks like the AQCTLA register gets updated immediately. Did you want an approximate timing of this "immediate" update?

Best,

Ryan Ma

Hi Ryan-san,

I appreciate your support.

However your experimental conditions are not clear for me.

Which is a source of ePWM1A is low,  trip-zone event(isr source) or CAU=AQ_CLEAR ?

And what is CMPA setting value ?

I believe that perhaps the experiment you intended was below.

CAU is updated before a timing of CTR=CMPA.

>Did you want an approximate timing of this "immediate" update?

I think that CAU/CAD active setting is updated immediately when sw set a value on CAU/CAD register.
I need the register specification of F28335. It was designed by TI hardware engineer.

If its specification is not provide to a user, could you please close this issue ?

Best regards,

Hidehiko