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TMS320F280025C: Power rail design inquiry and power sequence

Part Number: TMS320F280025C
Other Parts Discussed in Thread: TPD1E01B04

Hi

Customer is designing this part is their end equipment and has some design inquiries. The MCU is used to control few AC relays on board. Notice there is +/-50V <5ns of transient spikes observed on VDDIO / VDDA (+3.3V) rails

Questions

1. Would this overstress the MCU and trigger and any protection ?

2. Does it helpful to deploy ESD/TVS on VDDIO / VDDA rails to suppress the transient spikes ? eg adding TPD1E01B04

3. Is there a max capacitance for VDD ? The reason of asking, when the design uses 10uF and decoupling 0.1uF per VDD pin (total ~40uF). This result 1.2V ramp down slower as no external device connected to 1.2V for discharge. This also cause the voltage level difference between VDD (+1.2V) and VDDIO (+3.3V) more than 0.3V during power down sequence for >10ms. Would this cause any concern?

Similarly to XRSn pin, we saw >0.3V voltage difference between VRSn pin and VDDIO pin during power down sequence, will this voltage difference potentially damage the MCU ?

Rgds
Kelvin

  • Notice there is +/-50V <5ns of transient spikes observed on VDDIO / VDDA (+3.3V) rails

    Generally, ringing is in the order of few tens to few hundreds of millivolts. +/- 50v is excessive. Do you know how this magnitude of ringing gets coupled on the supply lines?

    1. Would this overstress the MCU and trigger and any protection ?

    This would turn on the internal clamping diodes. As to whether it would "overstress" the MCU, I need to reach out to some experts on this.

    2. Does it helpful to deploy ESD/TVS on VDDIO / VDDA rails to suppress the transient spikes ? eg adding TPD1E01B04

    An external clamping diode would indeed be helpful if it could turn on sufficiently fast and dissipate the unwanted energy. 

    3. Is there a max capacitance for VDD ?

    I will get back to you on this. 

  • The VDD capacitance of 10uF is correct.  The voltage difference seen during power down is normal and will not be a problem.

    A 50V for any amount of time on VDDIO/VDDA can damage the device.  This needs to be clamped external to the device to keep VDDIO/VDDA within the Absolute Maximum table of the datasheet.

    Best regards,

    Jason

  • Kelvin,

    I misread your original post.  The proper VDD capacitance for this device is 10uF total (with 20% tolerance capacitors or few smaller 0.1uF decoupling capacitors is fine).  You can put up to 22uF nominal capacitance if desired.  This range of 10-22uF is needed for the stability of the internal voltage regulator.

    Best regards,

    Jason