Other Parts Discussed in Thread: TPD1E01B04
Hi
Customer is designing this part is their end equipment and has some design inquiries. The MCU is used to control few AC relays on board. Notice there is +/-50V <5ns of transient spikes observed on VDDIO / VDDA (+3.3V) rails
Questions
1. Would this overstress the MCU and trigger and any protection ?
2. Does it helpful to deploy ESD/TVS on VDDIO / VDDA rails to suppress the transient spikes ? eg adding TPD1E01B04
3. Is there a max capacitance for VDD ? The reason of asking, when the design uses 10uF and decoupling 0.1uF per VDD pin (total ~40uF). This result 1.2V ramp down slower as no external device connected to 1.2V for discharge. This also cause the voltage level difference between VDD (+1.2V) and VDDIO (+3.3V) more than 0.3V during power down sequence for >10ms. Would this cause any concern?
Similarly to XRSn pin, we saw >0.3V voltage difference between VRSn pin and VDDIO pin during power down sequence, will this voltage difference potentially damage the MCU ?
Rgds
Kelvin