Hello,
According to the errata, there is an issue with the PLL not being properly lock.
The PLLSTS[LOCKS] bit is set, but the PLL does not produce a clock.
TI recommends a minimum of five lock sequences in succession when the PLL is configured the first time after a power up.
A lock sequence means disabling the PLL, starting the PLL locking, and waiting for the LOCKS bit to set. After the final sequence,
the clock source is switched to use the PLL output as normal.
I have few questions regarding this for loop though:
- Why five attempts? Has this number shown the best success rate?
- Why not 10, 15, 20 attempts? What is the magic number?
- What is the duration of the locking sequence?
My understanding is that if the 5 attempts were not successful, the watchdog will eventually reset the device once the PLL is transitioned to be used as the SYSCLK because no clock would be present to execute instructions to reset the WD counter.
Laurent