Hi everybody,
What is the most simple and reliable way to determine that SPLL_1PH_SOGI_FLL is in lock state and successfully synchronized with input wave?
Now I compare u_Q[0] and u_D[0] and if Q component is less that 10% of D component then I consider that PLL is locked. But may be there is a better criteria?
Kind regards,
Alex
Hi Alex,
It should be known that the FLL module builds on top of the SOGI module. Withe the difference being that the quadrature and the error component are in phase when the center frequency is greater than the actual and out of phase when it is lower than the actual. See the block diagram in the API guide mentioned below.
Please see the DigitalPower Library API Guide located at https://dev.ti.com/tirex/explore/node?node=A__AK-ZgXfLkBjr9Pafs40lNw__digital_power_c2000ware_sdk_software_package__5C6SEVO__LATEST
Regards,
Ozino
Hi Alex
The simplest way I can think of is compare the actual waveform and sin(theta) generated by the PLL. If they are in phase, PLL is working well.
Other way is the check VQ. If PLL is locked, Vq should be 0.
I will need some time to study SPLL to provide you the answer in terms of u_Q[0] and u_D[0].
Please let me know if the above answer helps.
Thanks
Amir
