TMS320F28384S: Adding sysbios to the CM

Laura Battle

Part Number: TMS320F28384S
Other Parts Discussed in Thread: SYSBIOS, C2000WARE

Hi, I'm trying to add SYSBIOS to what is essentially the enet_lwip tcp sample TI project that I have been modifying.

I modified the cmd file in the enet_lwip file to contain this boot section, but there are many options so I'm pretty unsure of if this is correct or not:

SECTIONS
{
    boot : > CMBANK0_SECTOR0 PAGE = 0
    {
        -l"C:\ti\bios_6_83_00_18\packages\ti\targets\arm\rtsarm\lib\boot.aem4" <boot_cg.o28FP> (.text)
    }
}

I am getting compiler errors however that this is an unsupported device.

I have sysbios in my linker and library paths, and below are some of my project properties:

Any idea about what I might be missing here would be great, Thanks,

Laura

4 months ago

0 Whitney Dewey 4 months ago

TI__Mastermind 49040 points

Hi Laura,

I imported a BIOS example for F28384S and these are the settings it used:

It looks like it supports the generic device family name instead of specific part numbers in the platform field.

Do note that we no longer recommend using SYS/BIOS in new projects. If you can, consider using FreeRTOS instead. We have a port of it available in the latest versions of C2000Ware in the kernel directory.

Whitney

0 Laura Battle 4 months ago in reply to Whitney Dewey

Prodigy 30 points

Thanks for the answer, Whitney.

So I have a further question that goes under the same title. Now that I have added SYSBIOS to the CM and compiled successfully, I can no longer run the CM with the debugger.

Essentially I get the same error as on this e2e post, where it runs out of breakpoints upon trying to load the program and pause at the beginning of the main function. I followed the advice in the post. I hit debugger on CM and saw 0 breakpoints enabled:

C28xx_CPU1: GEL Output: 
Memory Map Initialization Complete
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
Cortex_M4_0: GEL Output: Memory Map Initialization Complete
Cortex_M4_0: GEL Output: Windowed Watchdog Enabled
Cortex_M4_0: GEL Output: UART0 Enabled
Cortex_M4_0: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
Cortex_M4_0: AutoRun: Target not run as breakpoint could not be set: _JobHardwareBreakpoint::ARM_DEBUG_V7M_fpb_add_breakpoint: FPB : All resources are in use.[25062]
Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Logical Breakpoints: 107

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Software Physical Breakpoints: 109

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Legacy Hardware Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated 55 Hardware Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Thread Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: Enabled: 0

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: Disabled: 5

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$IOE$$"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Process CIO

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$EXITE"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Terminate Program Execution

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "SVC_Handler"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Semi hosting

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$IO$$"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Process CIO

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$EXIT"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Terminate Program Execution

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

However if I run this same script when running the CM normally, it shows 2 breakpoints enabled:

Cortex_M4_0: AutoRun: Target not run as breakpoint could not be set: _JobHardwareBreakpoint::ARM_DEBUG_V7M_fpb_add_breakpoint: FPB : All resources are in use.[25062]
Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Logical Breakpoints: 122

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Software Physical Breakpoints: 121

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Legacy Hardware Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated 55 Hardware Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Thread Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: Enabled: 2

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Type: Breakpoint

Cortex_M4_0: Breakpoint Manager Dump: 			Location: "C$$IO$$" (0x219116)

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Process CIO

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Type: Breakpoint

Cortex_M4_0: Breakpoint Manager Dump: 			Location: "C$$EXIT" (0x213064)

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Terminate Program Execution

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: Disabled: 3

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$IOE$$"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Process CIO

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$EXITE"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Terminate Program Execution

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "SVC_Handler"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Semi hosting

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

I played with disabling the breakpoints as in this e2e post on the Cortex M4 for both projects like so (both the c28x project and the CM project give options for disabling breakpoints on the m4):

but at this point the project runs without pausing at the beginning of main. So I'm not able to debug anything as debugging doesn't seem work unless the specific sequence outlined in "debugging multiple cores" works, and I'm given no opportunity to load CM.out and then play the exe for CPU1 before playing the CM executable.

Weirdly if I run the dump breakpoints at this point (when it has started running without permission), it still shows as 2 being enabled:

C28xx_CPU1: GEL Output: 
Memory Map Initialization Complete
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
Cortex_M4_0: GEL Output: Memory Map Initialization Complete
Cortex_M4_0: GEL Output: Windowed Watchdog Enabled
Cortex_M4_0: GEL Output: UART0 Enabled
Cortex_M4_0: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Logical Breakpoints: 85

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Software Physical Breakpoints: 84

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Legacy Hardware Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated 55 Hardware Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: Total Allocated Thread Physical Breakpoints: 0

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: Enabled: 2

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Type: Breakpoint

Cortex_M4_0: Breakpoint Manager Dump: 			Location: "C$$IO$$" (0x219116)

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Process CIO

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Type: Breakpoint

Cortex_M4_0: Breakpoint Manager Dump: 			Location: 0x2134d8

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Finish Auto Run

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: Disabled: 3

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$EXITE"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Terminate Program Execution

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Type: Breakpoint

Cortex_M4_0: Breakpoint Manager Dump: 			Location: "C$$EXIT" (0x213064)

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Terminate Program Execution

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Cortex_M4_0: Breakpoint Manager Dump: 

Cortex_M4_0: Breakpoint Manager Dump: 	Hardware Configuration

Cortex_M4_0: Breakpoint Manager Dump: 		Location: "C$$IOE$$"

Cortex_M4_0: Breakpoint Manager Dump: 	Debugger Response

Cortex_M4_0: Breakpoint Manager Dump: 		Condition: 

Cortex_M4_0: Breakpoint Manager Dump: 		Skip Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 			Current Count: 0

Cortex_M4_0: Breakpoint Manager Dump: 		Action: Process CIO

Cortex_M4_0: Breakpoint Manager Dump: 	Miscellaneous

Cortex_M4_0: Breakpoint Manager Dump: 		Group: Default Group

Cortex_M4_0: Breakpoint Manager Dump: 		Name: 

Cortex_M4_0: Breakpoint Manager Dump: 	Breakpoint set by the system

Any software breakpoints I set are not hit and it doesn't allow me to set hardware breakpoints due to no resources. I've also tried different combinations of disabling hardware breakpoints on the CM to no avail.

In order to get a baseline, I went back to the original enet_lwip example provided in C2000 and added SYSBIOS to that and using the corresponding TI control card rather than my custom board, I get the same exact errors, no difference whatsoever, (in fact these screenshots and console logs are from that project), so this is not related to my particular board or application.

What changes can I make so that I'm able to run a sysbios-based CM containing the lwIP stack via the CCS debugger?

Thanks,

Laura

0 Whitney Dewey 4 months ago in reply to Laura Battle

TI__Mastermind 49040 points

In your screenshots, it shows the "Enable CIO function use" box still checked. If you uncheck that one, does it make any difference?

When you halt the application, where is it stuck? It's possible it's getting stuck somewhere in the pre-main() init code and that's why it's never halting at main(). What Boot module settings are you using in your SYS/BIOS cfg file?

I give some advice in this thread about integrating SYS/BIOS and C2000Ware examples. You can see if there's anything there that you may have missed.

Whitney

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28384S: Adding sysbios to the CM