Other Parts Discussed in Thread: C2000WARE, SYSCONFIG
Hello TI,
Am using LAUNCHXL-F28379D
Looking to perform some Logic Operations on ePWM outputs using Configurable Logic Block (CLB).
Example:

Is this realizable?
If so please advise.
Best,
Colin
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Hello TI,
Am using LAUNCHXL-F28379D
Looking to perform some Logic Operations on ePWM outputs using Configurable Logic Block (CLB).
Example:

Is this realizable?
If so please advise.
Best,
Colin
Hello Colin,
Yes, this is possible; you can refer to the "Global Signals and Mux Selection" table and "Peripheral Signal Multiplexer Table" table in the CLB Input/Output Connection section of the CLB chapter. The specific connections you point out are there, and in fact there is a CLB example that does something similar to this provided in C2000Ware (C2000Ware_5_00_00_00\driverlib\f2837xd\examples\cpu1\clb\clb_ex1_combinatorial_logic).
Best regards,
Omer Amir
Hello Colin,
We do not have any examples of using the FSM as a LUT I believe, is there a reason you need to do this? Based on the design you have in your initial post you need 3 2-input LUTs, which there are available for the F2837xD device. Are you needing an extra one? If so, it should be possible to create a 4-input LUT based on this detail in the technical reference manual:

In SysConfig, the 16-bit output equation is the "LUT Output Equation":

Best regards,
Omer Amir
Hi Omer,
Thanks for getting back to me and for the info.
After re-thinking it, I'm not sure using FSM as LUT will work for me.
I need multiple versions of original block shown in first email above.
The syscfg block for original block looked something like the following. This was done/used just to get familiar with CLB.
Latest version has a bit more detail.

The MCU (F28379D) I am using has 4 Tiles, I need 6.
We added some logic so I can get 6 from 4 tiles but, had to use 2 outputs from Tiles 0 and 1 each, to feed Tiles 2 and 3 respectively as inputs.
Was originally trying to avoid using outputs from one tile to feed another, this is why I inquired about the FSM's.
Am wondering if this would create a timing issue? Am hoping to program MCU soon to see what happens.
Best,
Colin
Hello Colin,
If you're concerned about any timing issues, you can always use the simulation feature of the CLB Tool. You can refer to this User's Guide for more details on how to set it up and utilize it. Just as a note too, inputs to the CLB which are synchronized (such as those coming from other CLB tiles), need to have the input pipeline filter enabled for these sorts of timing concerns. Please use the simulation tool and let me know if you have further questions.
Best regards,
Omer Amir