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TMS320F28377D: SCI serial flash programmer fail update application image, FMSTAT Register contents: 01010

Part Number: TMS320F28377D
Other Parts Discussed in Thread: ASH

Hi 

Hi experts,

 I have encountered this problem for few week, and cannot resolve it. Please give me a hand.
CCS Version: 12.1.0
Example used: F2837xD_sci_falsh_kernel, Boot Rom code

I moved boot rom code (SCI boot) to my project, flash kernel transferred successful, but application image program is failed.

FMSTAT Register contents: 01010

VOLTSTAT and PSUSP seem to be set.


printed log:

6

0

0

0

Bit rate /s of transfer was: 7090.728516

Application load successful!

Done waiting for application to download and boot...

SUCCESS of Command

ERROR Status: Not Recognized Error

ERROR Address: 0x82000

Error not recognized

Please refer to the Flash API documentation for further explanation of the error.

FMSTAT Register contents: 01010

 

What operation do you want to perform?

         1-DFU CPU1

         2-DFU CPU2

         3-Erase CPU1

         4-Erase CPU2

         5-Verify CPU1

         6-Verify CPU2

         7-Unlock CPU1 Zone 1

         8-Unlock CPU1 Zone 2

         9-Unlock CPU2 Zone 1

        10-Unlock CPU2 Zone 2

        11-Run CPU1

        12-Reset CPU1

        13-Run CPU1 and Boot CPU2

        14-Reset CPU1 and Boot CPU2

        15-Run CPU2

        16-Reset CPU2

         0-DONE

 

calling f021_SendPacket

 

Finished sending Packet... Received ACK to Packet... Downloading *****.txt to device...

Please give me some advice.

BR/Alvin

  • Hi Alvin,

    Does this error still occur when changing the memory begin location in the application program's linker cmd file?

    Thanks and regards,

    Charles

  • Hi Charles,

    You mean BEGIN section? What it can be?

    BEGIN            : origin = 0x080000, length = 0x000002

    Here is my CMD file, please review it.

    MEMORY
    {
    PAGE 0 :  /* Program Memory */
              /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
              /* BEGIN is used for the "boot to Flash" bootloader mode   */
    
       BEGIN           	: origin = 0x080000, length = 0x000002
       RAMM0           	: origin = 0x000122, length = 0x0002DE
       RAMD0           	: origin = 0x00B000, length = 0x000800
       RAMLS0          	: origin = 0x008000, length = 0x001000
       //RAMLS1          	: origin = 0x008800, length = 0x000800
       RAMLS2      		: origin = 0x009000, length = 0x000800
       RAMLS3      		: origin = 0x009800, length = 0x000800
       RAMLS4      		: origin = 0x00A000, length = 0x000800
       RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RESET           	: origin = 0x3FFFC0, length = 0x000002
    
       /* Flash sectors */
       FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
       FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
       FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
       FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
       FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
       FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
       FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
       FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
       FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
       FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
       FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
       FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
       FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
       FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
    
    PAGE 1 : /* Data Memory */
             /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
    
       BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
       RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
       RAMD1           : origin = 0x00B800, length = 0x000800
    
       RAMLS5      : origin = 0x00A800, length = 0x000800
    
       RAMGS0      : origin = 0x00C000, length = 0x001000
       RAMGS1      : origin = 0x00D000, length = 0x001000
       RAMGS2      : origin = 0x00E000, length = 0x001000
       RAMGS3      : origin = 0x00F000, length = 0x001000
       RAMGS4      : origin = 0x010000, length = 0x001000
       RAMGS5      : origin = 0x011000, length = 0x001000
       RAMGS6      : origin = 0x012000, length = 0x001000
       RAMGS7      : origin = 0x013000, length = 0x001000
       RAMGS8      : origin = 0x014000, length = 0x001000
       RAMGS9      : origin = 0x015000, length = 0x001000
       RAMGS10     : origin = 0x016000, length = 0x001000
       RAMGS11     : origin = 0x017000, length = 0x001000
       RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
       CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
       CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
    
    }
    
    SECTIONS
    {
       /* Allocate program areas: */
       .cinit              : > FLASHB      PAGE = 0, ALIGN(8)
       .text               : >> FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
       codestart           : > BEGIN       PAGE = 0, ALIGN(8)
       /* Allocate uninitalized data sections: */
       .stack              : > RAMM1       PAGE = 1
       .switch             : > FLASHB      PAGE = 0, ALIGN(8)
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
    
    #if defined(__TI_EABI__)
       .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
       .bss                : > RAMLS5,       PAGE = 1
       .bss:output         : > RAMLS3,       PAGE = 0
       .bss:cio            : > RAMLS5,       PAGE = 1
       .data               : > RAMLS5,       PAGE = 1
       .sysmem             : > RAMLS5,       PAGE = 1
       /* Initalized sections go in Flash */
       .const              : > FLASHB,       PAGE = 0,       ALIGN(8)
    #else
       .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
       .ebss               : >> RAMLS5 | RAMGS2 | RAMGS3,    PAGE = 1
       .esysmem            : > RAMLS5,       PAGE = 1
       .cio                : > RAMLS5,       PAGE = 1
       /* Initalized sections go in Flash */
       .econst             : > FLASHB    PAGE = 0, ALIGN(8)
    #endif
    
       Filter_RegsFile     : > RAMGS0,	   PAGE = 1
    
       SHARERAMGS0		: > RAMGS0,		PAGE = 1
       SHARERAMGS1		: > RAMGS1,		PAGE = 1
       ramgs0           : > RAMGS0,     PAGE = 1
       ramgs1           : > RAMGS1,     PAGE = 1
    
       .scratchpad      : > RAMLS2,           PAGE = 0
    
    #ifdef __TI_COMPILER_VERSION__
        #if __TI_COMPILER_VERSION__ >= 15009000
            #if defined(__TI_EABI__)
    /*
    			GROUP
    			{
    				.TI.ramfunc : {}
    				dclfuncs
    				Cla1Prog
    			}
    
                					LOAD = FLASHB,
                                     RUN = RAMLS0, // | RAMLS1,
                                     LOAD_START(RamfuncsLoadStart),
                                     LOAD_SIZE(RamfuncsLoadSize),
                                     LOAD_END(RamfuncsLoadEnd),
                                     RUN_START(RamfuncsRunStart),
                                     RUN_SIZE(RamfuncsRunSize),
                                     RUN_END(RamfuncsRunEnd),
                                     PAGE = 0, ALIGN(8)
                                     */
            #else
    /*            GROUP
    			{
    				.TI.ramfunc : {}
    				dclfuncs
    				Cla1Prog
    			}
                				LOAD = FLASHB,
                                 RUN = RAMLS0 , //| RAMLS1
                                 LOAD_START(_RamfuncsLoadStart),
                                 LOAD_SIZE(_RamfuncsLoadSize),
                                 LOAD_END(_RamfuncsLoadEnd),
                                 RUN_START(_RamfuncsRunStart),
                                 RUN_SIZE(_RamfuncsRunSize),
                                 RUN_END(_RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
                                 */
    
                    .TI.ramfunc : {}
                                  LOAD = FLASHC | FLASHD | FLASHE,
                                  RUN = RAMLS0 , //| RAMLS1
                                  LOAD_START(_RamfuncsLoadStart),
                                  LOAD_SIZE(_RamfuncsLoadSize),
                                  LOAD_END(_RamfuncsLoadEnd),
                                  RUN_START(_RamfuncsRunStart),
                                  RUN_SIZE(_RamfuncsRunSize),
                                  RUN_END(_RamfuncsRunEnd),
                                  PAGE = 0, ALIGN(8)
    
                    dclfuncs :
                                  LOAD = FLASHC | FLASHD | FLASHE,
                                  RUN = RAMLS0 , //| RAMLS1
                                  LOAD_START(_DclfuncsLoadStart),
                                  LOAD_SIZE(_DclfuncsLoadSize),
                                  LOAD_END(_DclfuncsLoadEnd),
                                  RUN_START(_DclfuncsRunStart),
                                  RUN_SIZE(_DclfuncsRunSize),
                                  RUN_END(_DclfuncsRunEnd),
                                  PAGE = 0, ALIGN(8)
                    Cla1Prog :
                                  LOAD = FLASHC | FLASHD | FLASHE,
                                  RUN = RAMLS0 , //| RAMLS1
                                  LOAD_START(_Cla1funcsLoadStart),
                                  LOAD_SIZE(_Cla1funcsLoadSize),
                                  LOAD_END(_Cla1funcsLoadEnd),
                                  RUN_START(_Cla1funcsRunStart),
                                  RUN_SIZE(_Cla1funcsRunSize),
                                  RUN_END(_Cla1funcsRunEnd),
                                  PAGE = 0, ALIGN(8)
    
            #endif
        #else
       ramfuncs            : LOAD = FLASHB,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    
    #endif
    
       /* The following section definitions are required when using the IPC API Drivers */
        GROUP : > CPU1TOCPU2RAM, PAGE = 1
        {
            PUTBUFFER
            PUTWRITEIDX
            GETREADIDX
        }
    
        GROUP : > CPU2TOCPU1RAM, PAGE = 1
        {
            GETBUFFER :    TYPE = DSECT
            GETWRITEIDX :  TYPE = DSECT
            PUTREADIDX :   TYPE = DSECT
        }
    
       /* The following section definition are for SDFM examples */
       Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
       Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
       Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
       Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
       Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

  • Hi,

    Yes, does the error still occur when changing the flash section? Currently Flash Section B is at 0x82000 of memory. 

    Thanks,

    Charles

  • Hi Charles,

    The DSP's OTP registers may be changed. The upgrading is successful when i use another DSP.

    Thanks for your support.

    BR/Alvin