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TIDM-02013: SR control implementation

Part Number: TIDM-02013

Hi Champ,

I am asking for my customer about the SR control implementation in TIDM-02013. 

(1). Is the the control mechanism of SR is to compare ISEC_TANK nearly to 0A, then shutdown the SR ?

(2). Can SR enable and have the duty in soft-start way ? If yes, we could determine the duty, correct ?

(3). SR is a trigger of half-bridge PWM, can it be delayed ?

(4). The normal frequency is implemented at 500kHz. Calculated at 120MHz, so is the Period only 120 Count due to lower resolution set in up-down mode, correct ?

Thanks for the expert's comment here.

Regards,

Johnny

  • 1/3.

     CLLLC_ISEC_TANK_DACHVAL and  CLLLC_ISEC_TANK_DACLVAL control the PWM output. These are adjustable. I do not believe there is a specific "delay" but you can increase or decrease the DAC value slightly to provide delay or advance to the timing. (this of course assumes some slope to your current).

    2.The SRs could be ramped if desired, but i don't believe this was done in the design.

    4. This is a variable frequency design which could be as high as 800kHz. ePWM runs at 120MHz, so 1/120MHz is your resolution. You can calculate the number of time divisions based on the desired carrier frequency from that.