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TMS320F28379S: Reg. How to extend duty of PWM Sync out (EXTSYNCOUT) pulse width.

Part Number: TMS320F28379S

Hi,

 

Sub : Need to extend duty of PWM Sync out (EXTSYNCOUT) pulse width.

 

Requirement :

We have used EPWM6 for that EXTSYNCIN1 as sync input.

Our pwm switching frequency is 20KHZ

Base clock for PWM is sysclk = 200MHZ

 

For this configuration:

From the data sheet/TRM of TMS320F28379s controller, in the attached image the EXTSYNCOUT pulse duty is “pulse stretched(8 PLLSYSCLK)”. Which means as per my Configuration (PLLSYSCLK  = 200MHz). My EXTSYNCOUT pulse width period will be of  40 nano Seconds

 

PLLSYSCLK  = 1/200MHz = 5 nano seconds,

8 x PLLSYSCLK  = 8 * 5nS = 40 nano Seconds.

 

And I’m getting the pulse width exactly for 40nS(MHz) once in the 50uSeconds , attached the image below, (Oscilloscope Captured)

But in my application, I need the PWM_SYNC_IN pulse width to be at least 50% of period, So that I can use the proper filter to eliminate the Glitches in the Sync pulse for my hardware configuration.

  

System details:

I am using TMS320F28379s C2000 series micro controller and I’m trying to sync the PWM pulse between the two micro controllers considering one as a master (which sends the PWM_SYNC_OUT pulse) and another as a slave controller (i.e it receives the as PWM_SYNC_IN) - ( This is for the Inverter application)

 

I need to sync the PWM6A & PWM6B of the Master & Slave controllers. Code configuration are as follows controller System Clock is 200MHz, to generate the 20KHz (TBPRD = 5000) PWM Switching Frequency on the PWM6A & PWMB. Counter mode is in the UPDOWN counter Mode (/\/\/\/\).

Question : How to extend the EXTSYNCOUT Pulse width ?

 

  • Hi Rajamurugan,

    Pulse stretching cannot be done through the EPWM module, but you can look into implementing the CLB to create this behavior. While you cannot route the actual EPWM6 SYNC_OUT pulse to the CLB, you could use the TBCTR = 0 or TBCTR = PRD events of the master PWM to start a counter in the CLB that would emulate a stretched sync pulse. The CLB could drive an output GPIO signal high (the start of your extended sync pulse), and the counter can be set to last 50% of the duty cycle. When the timer expires, the output would go low again (the end of the extended sync pulse). This CLB output signal can be routed to the slave PWM as the SYNC_IN signal. Please note that this signal chain may produce a slight delay as it passes through these modules which you could also use phaseshift to correct for. In terms of board design: if you wish to use only a single-ended GPIO to issue the sync signal between the master and slave, take care to avoid cross talk and noise from nearby fast-switching signals. If these controllers are near to each other, this is less of a concern, but longer GPIO traces can increase noise. Let me know if you have further questions here.

    Regards,

    Allison