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TMS320F28034: The PWM issue

Part Number: TMS320F28034

Hi,

We use the TMS320F28034PNT in the H-bright circuit, and the frq. is 60MHz, now, we set the Controlling a Peak Current Mode Controlled Buck Module, and the PWM output by the comparator,

But the PWM has a peak noise in one cyclic, please refer to below picture:

Please kindly review the epwm.C and comp.c file and advise if there are any error, thanks.

  • Hi Zhang,

    Could you provide the epwm.c and comp.c file? It appears one of your PWM outputs (CH1) has a very clean signal while the other output (CH2) is very noisy. Are you referring to an app note or reference design when you mention "Controlling a Peak Current Mode Controlled Buck Module"?

    Thank you,

    Luke

  • Hi Zhang,

    Could you clarify whether the very short pulse on CH1 and CH2 is intentional, or should all pulses be the same width?

    Thank you,

    Luke

  • Hi Luke,

    Please refer to below epwm.c and comp.c file,

    1452.epwm.c
    #include "epwm.h"
    #include "main.h"
    #include "spll.h"
    
    uint16_t comp1DacVal=1;
    uint16_t comp2DacVal=1;
    uint16_t epwm1Duty=0;
    uint16_t epwm2Duty=0;
    uint16_t epwm1Period=600;
    uint16_t epwm2Period=600;
    
    #define TWO_H_US	    12000
    #define FOUR_H_US		24000
    int16_t Epwm1_init(void);
    int16_t Epwm2_init(void);
    int16_t Epwm3_init(void);
    
    interrupt void Epwm1_ISR(void);
    
    int16_t Epwm_init(void)
    {
        int16_t retval = 0;
    	
        retval = Epwm1_init();
        retval = Epwm2_init();
    	retval = Epwm3_init();
    	
        return retval;
    }
    
    int16_t Epwm1_init(void)
    {
    	int16_t retval = 0;
    
        EALLOW;
        GpioCtrlRegs.GPAMUX1.bit.GPIO0	= 1;
        GpioCtrlRegs.GPADIR.bit.GPIO0	= 1;
        EDIS;
    
    	// Time-Base Submodule
    	EPwm1Regs.TBCTL.bit.FREE_SOFT 	= 0x2;	//Free run
    	EPwm1Regs.TBCTL.bit.PHSDIR		= TB_UP;
    	EPwm1Regs.TBCTL.bit.CLKDIV		= TB_DIV1;
    	EPwm1Regs.TBCTL.bit.HSPCLKDIV	= TB_DIV1;
    	EPwm1Regs.TBCTL.bit.SWFSYNC		= 0x0;	// no force sync pulse
    	EPwm1Regs.TBCTL.bit.SYNCOSEL	= TB_CTR_ZERO;
    	EPwm1Regs.TBCTL.bit.PRDLD		= TB_SHADOW;
    	EPwm1Regs.TBCTL.bit.PHSEN		= TB_DISABLE;
    	EPwm1Regs.TBCTL.bit.CTRMODE		= TB_COUNT_UP;
    	EPwm1Regs.TBSTS.bit.CTRMAX		= 0x1;	// clear the latched event
    	EPwm1Regs.TBSTS.bit.SYNCI		= 0x1;	// clear the latched event
    	EPwm1Regs.TBPHS.all				= 0x0;	
    	EPwm1Regs.TBCTR					= 0;
    	EPwm1Regs.TBPRD					= 600;	// period
    	
    	// Counter-Compare Submodule
    	EPwm1Regs.CMPCTL.bit.SHDWBMODE	= CC_SHADOW;
    	EPwm1Regs.CMPCTL.bit.SHDWAMODE	= CC_SHADOW;
    	EPwm1Regs.CMPCTL.bit.LOADBMODE	= CC_CTR_ZERO;
    	EPwm1Regs.CMPCTL.bit.LOADAMODE	= CC_CTR_ZERO;
    	EPwm1Regs.CMPA.all				= 0x0;	// duty
    	EPwm1Regs.CMPB					= 0x0;
    
    	// Action-Qualifier Submodule
    	EPwm1Regs.AQCTLA.bit.CBD		= AQ_NO_ACTION;
    	EPwm1Regs.AQCTLA.bit.CBU		= AQ_NO_ACTION;
    	EPwm1Regs.AQCTLA.bit.CAD		= AQ_NO_ACTION;
    	EPwm1Regs.AQCTLA.bit.CAU		= AQ_CLEAR;
    	EPwm1Regs.AQCTLA.bit.PRD		= AQ_NO_ACTION;
    	EPwm1Regs.AQCTLA.bit.ZRO		= AQ_SET;
    	EPwm1Regs.AQCTLB.all			= 0x0;	// Do nothing
    	EPwm1Regs.AQSFRC.all			= 0x0;
    	EPwm1Regs.AQCSFRC.all			= 0x0;
    	
    	// Dead-Band Submodule
    	EPwm1Regs.DBCTL.bit.HALFCYCLE	= 0x0;	// Full cycle clocking enabled
    	EPwm1Regs.DBCTL.bit.IN_MODE		= DBA_ALL;
    	EPwm1Regs.DBCTL.bit.POLSEL		= DB_ACTV_HI;
    	EPwm1Regs.DBCTL.bit.OUT_MODE	= DB_DISABLE;
    	EPwm1Regs.DBRED					= 0x0;
    	EPwm1Regs.DBFED					= 0x0;
    	
        EALLOW;
    	// Trip-Zone Submodule
    	EPwm1Regs.TZSEL.bit.DCBEVT1		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.DCAEVT1		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.OSHT6		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.OSHT5		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.OSHT4		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.OSHT3		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.OSHT2		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.OSHT1		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.DCBEVT2		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.DCAEVT2		= TZ_ENABLE;
    	EPwm1Regs.TZSEL.bit.CBC6		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.CBC5		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.CBC4		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.CBC3		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.CBC2		= TZ_DISABLE;
    	EPwm1Regs.TZSEL.bit.CBC1		= TZ_DISABLE;
    	EPwm1Regs.TZDCSEL.bit.DCBEVT2	= TZ_EVT_DISABLE;
    	EPwm1Regs.TZDCSEL.bit.DCBEVT1	= TZ_EVT_DISABLE;
    	EPwm1Regs.TZDCSEL.bit.DCAEVT2	= TZ_DCAH_HI;
    	EPwm1Regs.TZDCSEL.bit.DCAEVT1	= TZ_EVT_DISABLE;
    	EPwm1Regs.TZCTL.bit.DCBEVT2		= TZ_NO_CHANGE;
    	EPwm1Regs.TZCTL.bit.DCBEVT1		= TZ_NO_CHANGE;
    	EPwm1Regs.TZCTL.bit.DCAEVT2		= TZ_FORCE_LO;
    	EPwm1Regs.TZCTL.bit.DCAEVT1		= TZ_NO_CHANGE;
    	EPwm1Regs.TZCTL.bit.TZB			= TZ_NO_CHANGE;
    	EPwm1Regs.TZCTL.bit.TZA			= TZ_FORCE_LO;
    	EPwm1Regs.TZEINT.all			= 0x0;	// disable interrupts
    //	EPwm1Regs.TZFLG
    	EPwm1Regs.TZCLR.all				= 0x7f;	// clear all interrupts
    	EPwm1Regs.TZFRC.all				= 0x0;
        EDIS;
    
    	// Event-Trigger Submodule
    	EPwm1Regs.ETSEL.bit.SOCBEN		= 0x0;	// Disable EPWMxSOCB
    	EPwm1Regs.ETSEL.bit.SOCAEN		= 0x0;	// Disable EPWMxSOCA
    	EPwm1Regs.ETSEL.bit.INTEN		= 0x1;	// Enable EPWM1_INT generation
    	EPwm1Regs.ETSEL.bit.INTSEL		= 0x2;	// Enable event TBCTR = TBPRD
    	EPwm1Regs.ETPS.bit.SOCBPRD		= 0x0;	// Disable the SOCB event counter
    	EPwm1Regs.ETPS.bit.SOCAPRD		= 0x0;	// Disable the SOCA event counter
    	EPwm1Regs.ETPS.bit.INTPRD		= 0x1;	// Generate an interrupt on the first event
    //	EPwm1Regs.ETFLG.all
    	EPwm1Regs.ETCLR.bit.SOCB		= 0x1;	// Clears the ETFLG[SOCB] flag bit
    	EPwm1Regs.ETCLR.bit.SOCA		= 0x1;	// Clears the ETFLG[SOCA] flag bit
    	EPwm1Regs.ETCLR.bit.INT			= 0x1;	// Clears the ETFLG[INT] flag bit
    	EPwm1Regs.ETFRC.all				= 0x0;
    
    	// PWM-Chopper Submodule
    	EPwm1Regs.PCCTL.bit.CHPEN		= CHP_DISABLE;
    
        EALLOW;	
    	// Digital Compare Submodule
    	EPwm1Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 0x0;
    	EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x0;
    	EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL = 0x0;	
    	EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT;	
    	
    	EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
    	EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
    	EPwm1Regs.DCACTL.bit.EVT1SYNCE = 0x0; // SYNC Generation Disabled
    	EPwm1Regs.DCACTL.bit.EVT1SOCE = 0x0; // SOC Generation Disabled
    	EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;
    	EPwm1Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; //Source Is DCAEVT1 Signal
    
    	EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0x0;
    	EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = 0x0;
    	EPwm1Regs.DCBCTL.bit.EVT1SYNCE = 0x0;
    	EPwm1Regs.DCBCTL.bit.EVT1SOCE = 0x0;
    	EPwm1Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0x0;
    	EPwm1Regs.DCBCTL.bit.EVT1SRCSEL = 0x0;
    	
    	EPwm1Regs.DCFCTL.all			= 0x0;
    	EPwm1Regs.DCCAPCTL.all			= 0x0;
    	EPwm1Regs.DCFOFFSET				= 0x0;
    	EPwm1Regs.DCFOFFSETCNT			= 0x0;
    	EPwm1Regs.DCFWINDOW				= 0x0;
    	EPwm1Regs.DCFWINDOWCNT			= 0x0;
    //	EPwm1Regs.DCCAP
    
    	EPwm1Regs.HRPCTL.bit.PWMSYNCSEL = 0x0;
        EDIS;
    
        EALLOW;
    	PieVectTable.EPWM1_INT = &Epwm1_ISR;
        EDIS;
    
    	PieCtrlRegs.PIEIER3.bit.INTx1	= 0x1;
    	IER |= M_INT3;
    
    	return retval;
    }
    
    int16_t Epwm2_init(void)
    {
    	int16_t retval = 0;
    
        EALLOW;
        GpioCtrlRegs.GPAMUX1.bit.GPIO2	= 1;
        GpioCtrlRegs.GPADIR.bit.GPIO2	= 1;
        EDIS;
    
    	// Time-Base Submodule
    	EPwm2Regs.TBCTL.bit.FREE_SOFT 	= 0x2;	    // Free run
    	EPwm2Regs.TBCTL.bit.PHSDIR		= TB_UP;	// Count up after the synchronization event
    	EPwm2Regs.TBCTL.bit.CLKDIV		= TB_DIV1;	// = 1
    	EPwm2Regs.TBCTL.bit.HSPCLKDIV	= TB_DIV1;	// = 1
    	EPwm2Regs.TBCTL.bit.SWFSYNC		= 0x0;	    // no force sync pulse
    	EPwm2Regs.TBCTL.bit.SYNCOSEL	= TB_SYNC_DISABLE;	// Disable EPWMxSYNCO signal
    	EPwm2Regs.TBCTL.bit.PRDLD		= TB_SHADOW;	// TBPRD is loaded from its shadow register
    	EPwm2Regs.TBCTL.bit.PHSEN		= TB_ENABLE;	// CTR Load From Phase Register enable
    	EPwm2Regs.TBCTL.bit.CTRMODE		= TB_COUNT_UP;	// Up-down-count mode
    	EPwm2Regs.TBSTS.bit.CTRMAX		= 0x1;	// clear the latched event
    	EPwm2Regs.TBSTS.bit.SYNCI		= 0x1;	// clear the latched event
    	EPwm2Regs.TBPHS.all				= 0x0;	
    	EPwm2Regs.TBCTR					= 0x0;
    	EPwm2Regs.TBPRD					= 600;	// period
    	
    	// Counter-Compare Submodule
    	EPwm2Regs.CMPCTL.bit.SHDWBMODE	= CC_SHADOW;	// Shadow mode
    	EPwm2Regs.CMPCTL.bit.SHDWAMODE	= CC_SHADOW;	// Shadow mode
    	EPwm2Regs.CMPCTL.bit.LOADBMODE	= CC_CTR_ZERO;	// Load on CTR = Zero
    	EPwm2Regs.CMPCTL.bit.LOADAMODE	= CC_CTR_ZERO;	// Load on CTR = Zero	
    	EPwm2Regs.CMPA.all				= 0x0;	// duty
    	EPwm2Regs.CMPB					= 0x0;
    
    	// Action-Qualifier Submodule
    	EPwm2Regs.AQCTLA.bit.CBD		= AQ_NO_ACTION;	// Do nothing
    	EPwm2Regs.AQCTLA.bit.CBU		= AQ_NO_ACTION;	// Do nothing
    	EPwm2Regs.AQCTLA.bit.CAD		= AQ_NO_ACTION;	// Do nothing
    	EPwm2Regs.AQCTLA.bit.CAU		= AQ_CLEAR;	// force EPWM1A output high
    	EPwm2Regs.AQCTLA.bit.PRD		= AQ_NO_ACTION;	// Do nothing
    	EPwm2Regs.AQCTLA.bit.ZRO		= AQ_SET;	// Do nothing
    	EPwm2Regs.AQCTLB.all			= 0x0;	// Do nothing
    	EPwm2Regs.AQSFRC.all			= 0x0;
    	EPwm2Regs.AQCSFRC.all			= 0x0;
    	
    	// Dead-Band Submodule
    	EPwm2Regs.DBCTL.bit.HALFCYCLE	= 0x0;	// Full cycle clocking enabled
    	EPwm2Regs.DBCTL.bit.IN_MODE		= DBA_ALL;
    	EPwm2Regs.DBCTL.bit.POLSEL		= DB_ACTV_HI;
    	EPwm2Regs.DBCTL.bit.OUT_MODE	= DB_DISABLE;	// Bypass DB submodule
    	EPwm2Regs.DBRED					= 0x0;
    	EPwm2Regs.DBFED					= 0x0;
    
        EALLOW;	
    	// Trip-Zone Submodule
    	EPwm2Regs.TZSEL.bit.DCBEVT1 	= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.DCAEVT1 	= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.OSHT6		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.OSHT5		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.OSHT4		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.OSHT3		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.OSHT2		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.OSHT1		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.DCBEVT2 	= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.DCAEVT2 	= TZ_ENABLE;
    	EPwm2Regs.TZSEL.bit.CBC6		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.CBC5		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.CBC4		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.CBC3		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.CBC2		= TZ_DISABLE;
    	EPwm2Regs.TZSEL.bit.CBC1		= TZ_DISABLE;
    	EPwm2Regs.TZDCSEL.bit.DCBEVT2	= TZ_EVT_DISABLE;
    	EPwm2Regs.TZDCSEL.bit.DCBEVT1	= TZ_EVT_DISABLE;
    	EPwm2Regs.TZDCSEL.bit.DCAEVT2	= TZ_DCAH_HI;
    	EPwm2Regs.TZDCSEL.bit.DCAEVT1	= TZ_EVT_DISABLE;
    	EPwm2Regs.TZCTL.bit.DCBEVT2 	= TZ_NO_CHANGE;
    	EPwm2Regs.TZCTL.bit.DCBEVT1 	= TZ_NO_CHANGE;
    	EPwm2Regs.TZCTL.bit.DCAEVT2 	= TZ_FORCE_LO;
    	EPwm2Regs.TZCTL.bit.DCAEVT1 	= TZ_NO_CHANGE;
    	EPwm2Regs.TZCTL.bit.TZB 		= TZ_NO_CHANGE;
    	EPwm2Regs.TZCTL.bit.TZA 		= TZ_FORCE_LO;
    	EPwm2Regs.TZEINT.all			= 0x0;	// disable interrupts
    //	EPwm2Regs.TZFLG
    	EPwm2Regs.TZCLR.all 			= 0x7f; // clear all interrupts
    	EPwm2Regs.TZFRC.all 			= 0x0;
        EDIS;
    	
    	// Event-Trigger Submodule
    	EPwm2Regs.ETSEL.bit.SOCBEN		= 0x0;	// Disable EPWMxSOCB
    	EPwm2Regs.ETSEL.bit.SOCAEN		= 0x0;	// Disable EPWMxSOCA
    	EPwm2Regs.ETSEL.bit.INTEN		= 0x0;	// Disable EPWMx_INT generation
    	EPwm2Regs.ETPS.bit.SOCBPRD		= 0x0;	// Disable the SOCB event counter
    	EPwm2Regs.ETPS.bit.SOCAPRD		= 0x0;	// Disable the SOCA event counter
    	EPwm2Regs.ETPS.bit.INTPRD		= 0x0;	// Disable the interrupt event counter
    //	EPwm2Regs.ETFLG.all
    	EPwm2Regs.ETCLR.bit.SOCB		= 0x1;	// Clears the ETFLG[SOCB] flag bit
    	EPwm2Regs.ETCLR.bit.SOCA		= 0x1;	// Clears the ETFLG[SOCA] flag bit
    	EPwm2Regs.ETCLR.bit.INT			= 0x1;	// Clears the ETFLG[INT] flag bit
    	EPwm2Regs.ETFRC.all				= 0x0;
    
    	// PWM-Chopper Submodule
    	EPwm2Regs.PCCTL.bit.CHPEN		= CHP_DISABLE;	// disable (bypass) PWM choppor
    	
        EALLOW;	
    	// Digital Compare Submodule
    	EPwm2Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 0x0;
    	EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x0;
    	EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = 0x0;	
    	EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP2OUT;	
    	
    	EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;
    	EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
    	EPwm2Regs.DCACTL.bit.EVT1SYNCE = 0x0; // SYNC Generation Disabled
    	EPwm2Regs.DCACTL.bit.EVT1SOCE = 0x0; // SOC Generation Disabled
    	EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;
    	EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; //Source Is DCAEVT1 Signal
    
    	EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0x0;
    	EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = 0x0;
    	EPwm2Regs.DCBCTL.bit.EVT1SYNCE = 0x0;
    	EPwm2Regs.DCBCTL.bit.EVT1SOCE = 0x0;
    	EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0x0;
    	EPwm2Regs.DCBCTL.bit.EVT1SRCSEL = 0x0;
    	
    	EPwm2Regs.DCFCTL.all			= 0x0;
    	EPwm2Regs.DCCAPCTL.all			= 0x0;
    	EPwm2Regs.DCFOFFSET 			= 0x0;
    	EPwm2Regs.DCFOFFSETCNT			= 0x0;
    	EPwm2Regs.DCFWINDOW 			= 0x0;
    	EPwm2Regs.DCFWINDOWCNT			= 0x0;
    //	EPwm2Regs.DCCAP
    
    	EPwm2Regs.HRPCTL.bit.PWMSYNCSEL = 0x0;
        EDIS;
    
    	return retval;
    }
    // uint32_t pwmCnt = 0;
    
    int16_t Epwm3_init(void)
    {
    	int16_t retval=0;
    	
    	return retval;
    }
    
    #pragma CODE_SECTION(Epwm1_ISR, "ramfuncs");
    interrupt void Epwm1_ISR(void)
    {
    //	uint32_t theta;
    //	theta = spll1.theta;
    	
    #if 1
    	int32_t halfGridPeriod;
    	int32_t count = ECap1Regs.TSCTR;
    	count += PARAMT; //delay uS
    	if(count > gridPeriod)count -= gridPeriod;
    
    	halfGridPeriod = gridPeriod >> 1;
    
    	if(count < halfGridPeriod)
    	{
    		if(count>halfGridPeriod-TWO_H_US)
    		{
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;	// 4 mos all off
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}
    		else if(count>halfGridPeriod-FOUR_H_US)
    		{
    			GpioDataRegs.GPBCLEAR.all = 0x0200;	// GPIO41=0;
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}
    		else if(count>TWO_H_US)
    		{
    			GpioDataRegs.GPBSET.all = 0x01200;	// GPIO41=1; GPIO44=1;
    		}
    		else
    		{
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;	// 4 mos all off
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    
    		}
    	}
    	else
    	{
    		if(count>gridPeriod-TWO_H_US)
    		{
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;	// 4 mos all off
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}
    		else if(count>gridPeriod-FOUR_H_US)
    		{
    			GpioDataRegs.GPBCLEAR.all = 0x0400;	//GPIO42=0;
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}
    		else if(count>halfGridPeriod+TWO_H_US)
    		{
    			GpioDataRegs.GPBSET.all = 0x00C00;	//GPIO43=1; GPIO42=1;
    		}
    		else
    		{
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;	// 4 mos all off
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}
    	}
    #endif
    
    #if 0
    	if(theta < _IQ15(3.14159265359))
    	{
    		if(theta > _IQ15(3.110176720771)){
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;	
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}else if(theta > _IQ15(2.905973157447)){
    			GpioDataRegs.GPBCLEAR.all = 0x200;
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}else if(theta > _IQ15(0.031415932819)){
    			GpioDataRegs.GPBSET.all = 0x1200;
    		}else{
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}
    	}else{
    		if(theta > _IQ15(6.251769374361)){
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}else if(theta > _IQ15(6.047565811036)){
    			GpioDataRegs.GPBCLEAR.all = 0x400;
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}else if(theta > _IQ15(3.173008586409)){
    			GpioDataRegs.GPBSET.all = 0x0C00;
    		}else{
    			GpioDataRegs.GPBCLEAR.all = 0x1E00;
    			comp1DacVal = 0;
    			comp2DacVal = 0;
    		}
    	}
    #endif
    
    	EPwm1Regs.CMPA.half.CMPA = epwm1Duty;
    	EPwm1Regs.TBPRD = epwm1Period;
    	
    	EPwm2Regs.CMPA.half.CMPA = epwm2Duty;
    	EPwm2Regs.TBPHS.half.TBPHS = epwm2Period>>1;
    	EPwm2Regs.TBPRD = epwm2Period;
    	
    //	Comp1Regs.DACVAL.bit.DACVAL = comp1DacVal;
    //	Comp2Regs.DACVAL.bit.DACVAL = comp2DacVal;
    	Comp1Regs.RAMPMAXREF_SHDW = comp1DacVal;	//comp1DacVal<<6;
    	Comp2Regs.RAMPMAXREF_SHDW = comp2DacVal;	//comp2DacVal<<6;
    	Comp1Regs.RAMPDECVAL_SHDW = slopeDecStep;
    	Comp2Regs.RAMPDECVAL_SHDW = slopeDecStep;
    
        EPwm1Regs.ETCLR.bit.INT = 1;
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
    }
    
    #pragma CODE_SECTION(Epwm3_ISR, "ramfuncs");
    interrupt void Epwm3_ISR(void)
    {
    	
    }
    
    
    comp.c
    #include "comp.h"
    
    int16_t Comp1_init(void);
    int16_t Comp2_init(void);
    
    int16_t slopeDecStep=0x0;
    
    int16_t Comp_init(void)
    {
    	int16_t retval = 0;
    	retval = Comp1_init();
    	retval = Comp2_init();
    	return retval;
    }
    
    int16_t Comp1_init(void)
    {
    	// how to trip EPWM1A
    
    	EALLOW;
    	GpioCtrlRegs.AIOMUX1.bit.AIO2 = 0x2; // comp1a
    	EDIS;
    	
    	EALLOW;
    	Comp1Regs.COMPCTL.bit.COMPDACEN = 0x1; // Internal Dac is Power On
    	Comp1Regs.COMPCTL.bit.SYNCSEL = 0x1; // Synchronous of output
    	Comp1Regs.COMPCTL.bit.QUALSEL = 0x2; // 3 clocks
    	Comp1Regs.COMPCTL.bit.CMPINV = 0x0; // No inverter
    	Comp1Regs.COMPCTL.bit.COMPSOURCE = 0x0; // Input connected to internal DAC
    
    //	Comp1Regs.COMPSTS
    	Comp1Regs.DACCTL.bit.FREE_SOFT = 0x2; // run free
    	Comp1Regs.DACCTL.bit.RAMPSOURCE = 0x0; // PWMSYNC1 is the source sync
    	Comp1Regs.DACCTL.bit.DACSOURCE = 0x1; // DAC controlled by RAMP
    	Comp1Regs.DACVAL.bit.DACVAL = 0x0; // ??
    //	Comp1Regs.RAMPMAXREF_ACTIVE
    	Comp1Regs.RAMPMAXREF_SHDW = 0x0; //
    //	Comp1Regs.RAMPDECVAL_ACTIVE
    	Comp1Regs.RAMPDECVAL_SHDW = slopeDecStep; //
    //	Comp1Regs.RAMPSTS
    	EDIS;
    
    	return 0;
    }
    
    int16_t Comp2_init(void)
    {
    	EALLOW;
    	GpioCtrlRegs.AIOMUX1.bit.AIO4 = 0x2; // comp2a
    	EDIS;
    
    	EALLOW;
    	Comp2Regs.COMPCTL.bit.COMPDACEN = 0x1; // Internal Dac is Power On
    	Comp2Regs.COMPCTL.bit.SYNCSEL = 0x1; // Synchronous of output
    	Comp2Regs.COMPCTL.bit.QUALSEL = 0x2; // 3 clocks
    	Comp2Regs.COMPCTL.bit.CMPINV = 0x0; // No inverter
    	Comp2Regs.COMPCTL.bit.COMPSOURCE = 0x0; // Input connected to internal DAC
    
    //	Comp2Regs.COMPSTS
    	Comp2Regs.DACCTL.bit.FREE_SOFT = 0x2; // run free
    	Comp2Regs.DACCTL.bit.RAMPSOURCE = 0x1; // PWMSYNC2 is the source sync
    	Comp2Regs.DACCTL.bit.DACSOURCE = 0x1; // DAC controlled by RAMP
    	Comp2Regs.DACVAL.bit.DACVAL = 0x0; // ??
    //	Comp2Regs.RAMPMAXREF_ACTIVE
    	Comp2Regs.RAMPMAXREF_SHDW = 0x0; //
    //	Comp2Regs.RAMPDECVAL_ACTIVE
    	Comp2Regs.RAMPDECVAL_SHDW = slopeDecStep; //
    //	Comp2Regs.RAMPSTS
    	EDIS;
    
    	return 0;
    }
    
    

    We have no idea for the "Controlling a Peak Current Mode Controlled Buck Module" because there are no detial information in the document;

    The short pulse on CH1 and CH2 are all pulses in the same width, so we don't know what is happen. thanks.

  • Hi Zhang,

    Before I look into the code, could you clarify what the issue is exactly. I see your waveform varies between a long and a short pulse. Is the expected behavior for the short pulses to be no pulse at all? Or is this not the issue?

    Is the issue the difference in noise between CH1 and CH2? If so, this is probably not a EPWM configuration issue since your PWM signals are identical aside from noise. The noise is likely due to how you're scoping your signal or some other hardware related issue.

    Thank you,

    Luke