[FAQ] TMS320F28003x,TMS320F28004x: Flash API usage advisory/errata

Below Errata Advisory is applicable for TMS320F28003x,TMS320F28004x devices with more than one flash bank.  We will add this advisory to the respective device errata document soon.  Also, we will update the flash programming examples in C2000Ware_5_02_00_00 (target release date is April 2024) to include the below discussed SW workaround.  

Flash Errata Advisory: Execution of Fapi_setActiveFlashBank() without disabling flash prefetch may cause ITRAP.

Details: Flash prefetch mechanism should be disabled only by the code executing from RAM and only when there is no any active fetch access to flash.  Fapi_setActiveFlashBank() disables the prefetch mechanism.  Any flash execution can result in ITRAP when the prefetch-disable process is in progress. Hence, prefetch should be disabled before executing Fapi_setActiveFlashBank().

Workaround: Disable the prefetch mechanism before calling Fapi_setActiveFlashBank().  Prefetch can be enabled after the execution of the Fapi_setActiveFlashBank().  Code that disables and enables the prefetch mechanism should be executed from RAM.  When this workaround is implemented, note that Fapi_setActiveFlashBank() can be executed from flash (not from the bank on which the erase/program operations are targeted) since prefetch is already disabled. 

Flash API usage examples provided in C2000Ware_5_02_00_00 (and onwards) depict the usage of this workaround.

Path to the TMS320F28003x example:

C2000Ware_5_02_00_00\driverlib\f28003x\examples\flash\flashapi_ex1_programming.c

Path to the TMS320F28004x example:

C2000Ware_5_02_00_00\driverlib\f28004x\examples\flash\flashapi_ex1_program_autoecc.c

In these examples, Flash_DisablePrefetch_SW_Workaround() is executed from RAM to disable the prefetch before calling Fapi_setActiveFlashBank().  Flash_EnablePrefetch_SW_Workaround() is executed from RAM to enable the prefetch after calling Fapi_setActiveFlashBank().

NOTE: Since C2000Ware_5_02_00_00 is not released yet, I provided the SW workaround implementation details below:

/* Implementation details: */

// As shown in below code snippet:
// Call Flash_DisablePrefetch_SW_Workaround() before Fapi_setActiveFlashBank().
// Call Flash_EnablePrefetch_SW_Workaround() after Fapi_setActiveFlashBank().


    //
    // Disable Flash prefetch before Fapi_setActiveFlashBank()
    //
    Flash_DisablePrefetch_SW_Workaround(FLASH0CTRL_BASE);

    //
    // Initialize the Flash banks and FMC for erase and program operations.
    // Fapi_setActiveFlashBank() function sets the Flash banks and FMC for
    // further Flash operations to be performed on the banks.
    //
    oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);

    if(oReturnCheck != Fapi_Status_Success)
    {
        //
        // Check Flash API documentation for possible errors
        //
        Example_Error(oReturnCheck);
    }

    //
    // Enable Flash prefetch after Fapi_setActiveFlashBank()
    //
    Flash_EnablePrefetch_SW_Workaround(FLASH0CTRL_BASE);
    
/* Below is the code for Flash_DisablePrefetch_SW_Workaround().  */

//*****************************************************************************
//
//! Disables flash prefetch mechanism and adds 7 cycle delay
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************

#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#else
#pragma CODE_SECTION(Flash_DisablePrefetch_SW_Workaround, ".TI.ramfunc");
#endif
void Flash_DisablePrefetch_SW_Workaround(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ASSERT(Flash_isCtrlBaseValid(ctrlBase));

    //
    // Disable flash prefetch
    //
    Flash_disablePrefetch(ctrlBase);

    //
    // Force a pipeline flush to ensure that the write to the last register
    // configured occurs before returning.
    //
    FLASH_DELAY_CONFIG;
}

/* Below is the code for Flash_EnablePrefetch_SW_Workaround()  */

//*****************************************************************************
//
//! Enables flash prefetch mechanism and adds 7 cycle delay
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************

#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#else
#pragma CODE_SECTION(Flash_EnablePrefetch_SW_Workaround, ".TI.ramfunc");
#endif
void Flash_EnablePrefetch_SW_Workaround(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ASSERT(Flash_isCtrlBaseValid(ctrlBase));

    //
    // Disable flash prefetch
    //
    Flash_enablePrefetch(ctrlBase);

    //
    // Force a pipeline flush to ensure that the write to the last register
    // configured occurs before returning.
    //
    FLASH_DELAY_CONFIG;
}