LAUNCHXL-F2800137: Peack current mode control

Hi Debora,

What topology are you using? Buck boost? LLC? PFC? I can assist with specific questions about how to configure the EPWM module to achieve the waveform you're looking for, but if you have questions about what peak current mode control is or how to implement it I may need to loop in another expert depending on your topology.

Thank you,

Luke

Hi, I am using buck boost topology. I configured EPWM7 with these actions qualifiers and trip zone:

//------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
//EPWM7B
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP);
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN);
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

//EPWM7A
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);
EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

//Trip zone event actions:
//TZB events can force EPWMxB
EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_U, EPWM_TZ_ADV_ACTION_LOW);
EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_D, EPWM_TZ_ADV_ACTION_DISABLE);
EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_DISABLE);

EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_U, EPWM_TZ_ADV_ACTION_DISABLE);
EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_D, EPWM_TZ_ADV_ACTION_LOW);
EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_DISABLE);

I configured also the CMPSS and the EPWM change the duty according to the input voltage and to the actions qualifiers. I have a DC that change from a minimum of 0% to a maximum of 98%. How I can set a maximum value and a minimum value for the duty cycle? For example minimum DC = 20% and maximum = 80%. 

Thank you in advance.

Hi Debora,

Are you updating your duty cycle in an ISR? If so, could you not just add a check in your code that makes sure the duty cycle is not configured to be greater than 80% or less than 20%?

The following app note may help you with implementing peak current mode control, although this was written for F2803x:

https://www.ti.com/lit/an/sprabe7a/sprabe7a.pdf?ts=1707255253699

Thank you,

Luke

Hi Luke, 

thank you for the response. I think to have configured a wrong peak current mode control, in fact I don't set any DC of the EPWM but the DC changes based on how I vary my input signal. Do you have any examples about peak current mode control? I have seen the application note, but for me it isn't clear. I am new to FW development on TI devices and also on Peak Current Mode Control. In the application note I find this code: 

I see only 2 lines and not 3. It is in page 23 of the application note. So, were the DC is set?

Could you have any documentations or example to set the EPWM and the CMPSS in the right way to implement the Peak Current Mode Control?

Thank you

Hi Luke,

I want to realize a PCMC and I have 2 analogs inputs, both reading by an ADC. One input goes in the CMP+ of the CMPSS1 while the other input is processing to set a ramp and a decrementVal as CMP- of the CMPSS. 

I want to have 2 ePWM signals from the CMPSS module: ePWM7A and ePWM7B in complementary mode.

When the output of the comparator gives 1, I want to set the EPWM7A to 1 and EPWM7B to 0. In other case I want that the ePWM is modulate according to my analog input CMP+ and the ramp which is CMP-.

Then I want to limit the maximum and the minimum duty cycle: for example max dc = 80% and minimum dc = 20%.

Thank you in advance

Hi Peter,

I try to implement you suggestions but I think to have problems during ePWM action qualifier, action adv qualifier action and setTripZoneAdvAction configuration for ePWM. So, I don't know if it doesn't work because my configuration is wrong.

Thank you

Hi Debora,

Do you need dead-band between the rising edge of your A output and falling edge of your B output? If so you could use the T1 action qualifier event that gets triggered by a trip signal from the CMPSS. The trip-zone module gets applied after the dead-band module, so you would need to use the action qualifier module to respond to the CMPSS signal to utilize dead-band.

You can set a minimum duty cycle via a blanking window that ends 20% into the period, and set a maximum duty cycle by having a CMPA action qualifier 80% into the period.

Let me know if you have additional questions.

Have you configured the EPWM XBAR and digital compare modules to connect your trip source to the EPWM? I would recommend using SysConfig to configure the EPWM and EPWM XBAR.

Thank you,

Luke

Hi Luke,

thank you for you reply. I think to have configured a maximum and a minimum DC with your suggestions.

Yes, I have configured EPWM7 connected to X-BAR (TRIPIN 4) and X-BAR connected to CMPSS.

But I have a question: In the peak current mode am I the one who has manually modify the Duty Cycle of the ePWM?

Thank you,

Debora

Hi Debora, 

Understood about the CMPSS usage. Typically customers will use the internal CMPSS DAC to generate the CMP- signal in order to save on pin usage, but our comparators do support external CMP- input. 

In Peak Current Mode control, the duty cycle of PWM is entirely controlled by the inductor feedback current so there should be no need to modify the duty cycle directly, you simply modify the peak current to control the duty and this is typically dictated by control effort from our digital control library in regulated closed-loop operation. 

The PWM switching scenario you described is different than that which is implemented in the TIDM-DC-DC-BUCK reference design. In the reference design, we have configured the rising edge of PWMA to occur at constant frequency and the falling edge of the PWMA is controlled by the peak current. Specifically, CMPSS input monitors the current and when feedback current exceeds configured peak current value, CMPSS output will go high (active high mode) which will clear PWMA output. It sounds like in your implementation, you need to use inverted mode of CMPSS.

Regards,

Peter

Hi Peter,

thank you for your reply.

Could you provide me an EPWM configuration with CMPSS configuration for my application?

Hi, 

I attached below my source code for EPWM configuration. Could you help me please? Where the errors are?

Thank you and best regards

void InitEpwm7()
{
    // Disable the ePWM time base clock before configuring the module
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //-------------------------------------------------------------------------------------------------------------------------------- SET EPWM PARAMETERS
    //EPWM with frequency of 100Khz and DC = 50%
    EPWM_setClockPrescaler(EPWM7_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBaseCounterMode(EPWM7_BASE, EPWM_COUNTER_MODE_UP);
    EPWM_setTimeBaseCounter(EPWM7_BASE, 0);
    EPWM_setTimeBasePeriod(EPWM7_BASE, TBPRD_PWM7);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_B, 499);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A, 499);

    //-------------------------------------------------------------------------------------------------------------------------------- ENABLE ADC Trigger
    EPWM_enableADCTrigger(EPWM7_BASE, EPWM_SOC_B);
    EPWM_setADCTriggerSource(EPWM7_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_U_CMPB);
    EPWM_setADCTriggerEventPrescale(EPWM7_BASE, EPWM_SOC_B, 1);


    //------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
    //EPWM7B
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //EPWM7A
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //-------------------------------------------------------------------------------------------------------------------------------- SET ACTIONS QUALIFIER FOR TRIP ZONE
    //Set DCBEVT2 as the trigger source
    EPWM_setActionQualifierT1TriggerSource(EPWM7_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);

    //DCBH = TRIP4 = CMPSS1 output
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);
    //DCBH = high
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_HIGH);

    // Set the source for digital compare filter as DCBEVT2
    EPWM_setDigitalCompareEventSource(EPWM7_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(EPWM7_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    //Select DCBEVT2 cycle by cycle trip
    EPWM_enableTripZoneSignals(EPWM7_BASE, EPWM_TZ_SIGNAL_DCBEVT2);

    //Enable the EPWM blanking window
    EPWM_enableDigitalCompareBlankingWindow(EPWM7_BASE);

    //Set the signal source that will be filtered
    EPWM_setDigitalCompareFilterInput(EPWM7_BASE, EPWM_DC_WINDOW_SOURCE_DCBEVT2);

    //Set the digital compare filter blanking pulse
    EPWM_setDigitalCompareBlankingEvent(EPWM7_BASE, EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);

    // Set the blanking window offset in TBCLK counts
    EPWM_setDigitalCompareWindowOffset(EPWM7_BASE, MAX_EPWM7B_PERIOD - 5);
    EPWM_setDigitalCompareWindowLength(EPWM7_BASE, 5);

    //Trip zone event actions:
    //TZB events can force EPWMxB
    EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_D, EPWM_TZ_ADV_ACTION_DISABLE);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_DISABLE);

    EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_U, EPWM_TZ_ADV_ACTION_DISABLE);
    EPWM_setTripZoneAdvAction(EPWM7_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_DISABLE);

    EPWM_selectCycleByCycleTripZoneClearEvent(EPWM7_BASE, EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);


    //Set the dead band to 150ns for rising and falling edges
    EPWM_setRisingEdgeDelayCount(EPWM7_BASE, 15);
    EPWM_setFallingEdgeDelayCount(EPWM7_BASE, 15);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_FED, true);
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMB);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMB);
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);


    EPWM_clearTripZoneFlag(EPWM7_BASE, (EPWM_TZ_INTERRUPT | EPWM_TZ_FLAG_DCBEVT1 | EPWM_TZ_FLAG_DCBEVT2));

    // Sync the ePWM time base clock
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    // Configure TRIP4 to be CTRIP1H using the ePWM X-BAR
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
}

Hi Debora,

Upon initial inspection of the code, I see that you have added AQ for EPWM7B output. If you are using active high complementary mode from the DeadBand module, you don't need to configure any AQ for the B output as that gets automatically generated from the A output. And it looks like you haven't configured a T2 source so a few of the AQ wouldn't execute. Also, the AQ for EPWM7A doesn't make sense to toggle high on Period and toggle low on Zero when in up-count mode. And T1 count down doesn't exist in up-count mode. 

Can you provide more details on your EPWM switching behavior. Assuming AHC, then you should only need to describe the A output and B will be complementary. 

You say that output of CMPSS equals 1 (invert mode) means that EPWM7A should be high. Then in PCMC we should expect that EPWM7A will go low when we hit the current threshold set by CMPSS. Do you expect that CMPSS will be low or high once we exceed the threshold? Assuming, then you need to invert trip signal coming into EPWM module

Regards,

Peter

Hi Peter,

thank you for the reply.

According to your comments, I modified my epwm configuration as shown below:

void InitEpwm7()
{
    // Disable the ePWM time base clock before configuring the module
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //-------------------------------------------------------------------------------------------------------------------------------- SET EPWM PARAMETERS
    //EPWM with frequency of 100Khz and DC = 80%
    EPWM_setClockPrescaler(EPWM7_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBaseCounterMode(EPWM7_BASE, EPWM_COUNTER_MODE_UP);
    EPWM_setTimeBaseCounter(EPWM7_BASE, 0);
    EPWM_setTimeBasePeriod(EPWM7_BASE, TBPRD_PWM7);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A, 799);

    //-------------------------------------------------------------------------------------------------------------------------------- ENABLE ADC Trigger
    EPWM_enableADCTrigger(EPWM7_BASE, EPWM_SOC_A);
    EPWM_setADCTriggerSource(EPWM7_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPA);
    EPWM_setADCTriggerEventPrescale(EPWM7_BASE, EPWM_SOC_A, 1);

    //-------------------------------------------------------------------------------------------------------------------------------- X BAR CONFIGURATION
    // Configure TRIP4 to be CTRIP1H using the ePWM X-BAR
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00);                                           //disable old mux configuration
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);

    //-------------------------------------------------------------------------------------------------------------------------------- DEAD BAND CONFIGURATION
    //Use EPWMA as the input for both RED and FED
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    //Set the RED and FED values
    EPWM_setFallingEdgeDelayCount(EPWM7_BASE, 15);                                  //dead band = 150ns --> DBFED = FED/Ttbclk = 150ns/(1/100MHz)
    EPWM_setRisingEdgeDelayCount(EPWM7_BASE, 15);                                   //dead band = 150ns --> DBRED = RED/Ttbclk = 150ns/(1/100MHz)
    //Invert only the falling edge delayed output (AHC = Active High Complementary)
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
    //Using the delayed signals instead of the original signals
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_FED, true);
    //Do not switch output A with output B
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_B, false);

    //-------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
}

Now I want to configure trip zone and trip event according to the output of the CMPSS, but it isn't clear for me how trip zone and trip event work.

I want to realize a peak current mode, so I want a PWM that change automatically its Duty Cycle and when the output of the CMPSS goes high, I want to force in low state the ePWMA and in high state the ePWMB.

Can you help me to provide a solution for my problem?

Thank you in advance,

Hi Peter,

could you tell me what the steps are to set up a trip zone? I would like that when the output of CMPSS is equal to 0, my PWMA is forced to 0 and my PWMB is forced to 0. But it is not clear for me how configure trip zone, action qualifier, TZA, TZB, DCAEVT1, DCAEVT2 works. 

Please help me. I don't know how to proceed with my FW.

Thank you,

Debora

Hi Debora,

Debora Previdi said:

When the output of the comparator gives 1, I want to set the EPWM7A to 1 and EPWM7B to 0. In other case I want that the ePWM is modulate according to my analog input CMP+ and the ramp which is CMP-.

Debora Previdi said:

so I want a PWM that change automatically its Duty Cycle and when the output of the CMPSS goes high, I want to force in low state the ePWMA and in high state the ePWMB.

These two statements are conflicting to me so it is difficult to understand how you would like to operate your PWMs in PCMC. Would you be able to provide some kind of diagram for how you would like to configure your CMPSS tripping? I would recommend to configure it such that when CMPSS is high, the PWMA signal trips low, as you will be able to use the similar PWM configuration as in our TIDM-DC-DC-BUCK reference design

Regards,

Peter

Hi Peter,

you're right. I made a bit of a mess when answering.

So, I want to realize a peak current mode. I want that when:

1) CMPSS output = 1 --> EPWM7A is 0 and EPWM7B is 1

2) CMPSS output = 0 --> EPWM7A and EPWM7B change automatically the DC according to the ramp.

Point 1) I managed to do but point 2) no.

I attached my source code for more details:

void InitEpwm7()
{
    // Disable the ePWM time base clock before configuring the module
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //-------------------------------------------------------------------------------------------------------------------------------- SET EPWM PARAMETERS
    //EPWM with frequency of 100Khz and DC = 80%
    EPWM_setClockPrescaler(EPWM7_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBaseCounterMode(EPWM7_BASE, EPWM_COUNTER_MODE_UP);
    EPWM_setTimeBaseCounter(EPWM7_BASE, 0);
    EPWM_setTimeBasePeriod(EPWM7_BASE, TBPRD_PWM7);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A, 799);

    //-------------------------------------------------------------------------------------------------------------------------------- ENABLE ADC Trigger
    EPWM_enableADCTrigger(EPWM7_BASE, EPWM_SOC_A);
    EPWM_setADCTriggerSource(EPWM7_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPA);
    EPWM_setADCTriggerEventPrescale(EPWM7_BASE, EPWM_SOC_A, 1);

    //-------------------------------------------------------------------------------------------------------------------------------- X BAR CONFIGURATION
    // Configure TRIP4 to be CTRIP1H using the ePWM X-BAR --> CMPSS1.CTRIPH as TRIP4 input
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00);                                           //disable old mux configuration
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
    XBAR_invertEPWMSignal(XBAR_TRIP4, false);

    //-------------------------------------------------------------------------------------------------------------------------------- DEAD BAND CONFIGURATION
    //Use EPWMA as the input for both RED and FED
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    //Set the RED and FED values
    EPWM_setFallingEdgeDelayCount(EPWM7_BASE, 15);                                  //dead band = 150ns --> DBFED = FED/Ttbclk = 150ns/(1/100MHz)
    EPWM_setRisingEdgeDelayCount(EPWM7_BASE, 15);                                   //dead band = 150ns --> DBRED = RED/Ttbclk = 150ns/(1/100MHz)
    //Invert only the falling edge delayed output (AHC = Active High Complementary)
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
    //Using the delayed signals instead of the original signals
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_FED, true);
    //Do not switch output A with output B
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_B, false);

    //-------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

    //-------------------------------------------------------------------------------------------------------------------------------- SET TRIP ZONE
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_LOW);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_LOW);
    EPWM_setDigitalCompareEventSource(EPWM7_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
    EPWM_setDigitalCompareEventSource(EPWM7_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
    EPWM_setDigitalCompareEventSyncMode(EPWM7_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
    EPWM_setDigitalCompareEventSyncMode(EPWM7_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_HIGH);
    EPWM_clearTripZoneFlag(EPWM7_BASE, (EPWM_TZ_FLAG_OST | EPWM_TZ_FLAG_DCAEVT2 | EPWM_TZ_FLAG_DCBEVT2 | EPWM_TZ_FLAG_CBC ));
}

Please help me to solve the issue.

Thank you in advance,

Debora

Hi Debora,

Debora Previdi said:

EPWM7A and EPWM7B change automatically the DC according to the ramp.

It will be helpful if you can provide visual diagram like below which shows how you expect the inductor current to operate in your design.

It sounds like you are wanting to have the CMPSS control both rising and falling edge of EPWM but to do this you would need to implement hysteretic control using two CMPSS. Suppose it may be easier to have the EPWM control the rising edge of the EPWM, and this is also the case since you look to be using the CBC trip of the PWM, so that CMPSS peak current trip will be released on every EPWM cycle. If you want to leverage CMPSS for the rising edge, you typically need to leverage a T2 action qualifier event.

Regards,

Peter

Hi Peter,

Thank you for your reply. 

I attached to this chat the behavior that I want for my application.

Please, give me an input to how configure my ePWM7. I do not have a fixed CMPSS[DACVAL].

I am not able to set action qualifier and trip zone and trip action.

Thank you in advance for the support.

Hi,

please there are any update about my problem?

Thank you.

Best regards.

Debora

Hi Debora,

The diagram you sent looks to be very similar to the scheme used in TIDM-DC-DC-BUCK.

Please refer to the following functions located in the buck_hal.c

BUCK_HAL_setupSyncBuckPwm

BUCK_HAL_setupSyncBuckPcmcTripAction

BUCK_HAL_setupPcmcCmpssTrip

These will match close with your setup, you will just need to adjust the EPWM and CMPSS bases depending on your hardware

Regards,

Peter

Hi Peter,

Thank you for the reply.

On Monday I will check the functions that you suggest to me and I will give you an answer. 

Thank you,

Best Regards,

Debora

Hi Peter! Great news!

Thanks to your last suggestion, my peak current mode works as I expected.

Thank you very much for the support!

But now I have a question: I fixed a maximum duty cycle thank you to your old suggestion to configure CMPA value to perform the maximum DC. But to configure a minimum DC, how I can do? In your last suggestion you told me to set blanking window, but when I configure blanking window the peak current mode does not work properly.

• It starts correctly at 20% DC, but when gradually decreasing the input voltage, it switches to 80% DC (3,28VDC) --> fig0 - fig1.
• If I continue to decrease the input voltage, it starts working as expected starting from 20% to 80% DC (starting from 2,73VDC to 0,084VDC).
• Except in one point that it switches at half of the PWM frequency when I reach 0,085VDC --> fig2 - fig3 - fig4.

The channels are:
CH2 = EPWM7A
CH3 = CTRIP OUT 
CH4 = EPWM7B
(Images.pdf contains snaps)

Vin input range: 0VDC to 3.3VDC

How I can fix the issue?

I attached my code below:

void InitEpwm7()
{
    // Disable the ePWM time base clock before configuring the module
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    EPWM_setEmulationMode(EPWM7_BASE, EPWM_EMULATION_FREE_RUN);

    //-------------------------------------------------------------------------------------------------------------------------------- SET EPWM PARAMETERS
    //EPWM with frequency of 100Khz and DC = 80%
    EPWM_setClockPrescaler(EPWM7_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBaseCounterMode(EPWM7_BASE, EPWM_COUNTER_MODE_UP);
    EPWM_setTimeBaseCounter(EPWM7_BASE, 0);
    EPWM_setTimeBasePeriod(EPWM7_BASE, TBPRD_PWM7);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A, 799);

    //-------------------------------------------------------------------------------------------------------------------------------- ENABLE ADC Trigger
    EPWM_enableADCTrigger(EPWM7_BASE, EPWM_SOC_A);
    EPWM_setADCTriggerSource(EPWM7_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPA);
    EPWM_setADCTriggerEventPrescale(EPWM7_BASE, EPWM_SOC_A, 1);

    //-------------------------------------------------------------------------------------------------------------------------------- X BAR CONFIGURATION
    // Configure TRIP4 to be CTRIP1H using the ePWM X-BAR --> CMPSS1.CTRIPH as TRIP4 input
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00);                                           //disable old mux configuration
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
    XBAR_invertEPWMSignal(XBAR_TRIP4, false);

    //-------------------------------------------------------------------------------------------------------------------------------- DEAD BAND CONFIGURATION
    //Use EPWMA as the input for both RED and FED
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    //Set the RED and FED values
    EPWM_setFallingEdgeDelayCount(EPWM7_BASE, 15);                                  //dead band = 150ns --> DBFED = FED/Ttbclk = 150ns/(1/100MHz)
    EPWM_setRisingEdgeDelayCount(EPWM7_BASE, 15);                                   //dead band = 150ns --> DBRED = RED/Ttbclk = 150ns/(1/100MHz)
    //Invert only the falling edge delayed output (AHC = Active High Complementary)
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
    //Using the delayed signals instead of the original signals
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_FED, true);
    //Do not switch output A with output B
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_B, false);

    //-------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

    //-------------------------------------------------------------------------------------------------------------------------------- SET TRIP ZONE
#define BLANKING_WINDOW
#ifdef BLANKING_WINDOW
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE);
    EPWM_setActionQualifierT1TriggerSource(EPWM7_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);

    EPWM_setDigitalCompareFilterInput(EPWM7_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT2);
    EPWM_setDigitalCompareBlankingEvent(EPWM7_BASE, EPWM_DC_WINDOW_START_TBCTR_ZERO);
    EPWM_setDigitalCompareWindowOffset(EPWM7_BASE, 0);
    EPWM_setDigitalCompareWindowLength(EPWM7_BASE, 200);
    EPWM_enableDigitalCompareBlankingWindow(EPWM7_BASE);
#else
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE);
    EPWM_setActionQualifierT1TriggerSource(EPWM7_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
#endif
}

Thank you a lot.

Best Regards,

Debora

Images.pdf

Hi Peter,

there are any news to help me with my issue?

I need to set a minimum duty cycle in my peak current mode. How I can do it? I tried to manually control the minimum duty cycle by reading the actual duty cycle and if the actual duty cycle is minor of 20% I force the DC = 20% but it doesn't work. 

Can you help me, please?

Thank you in advance,

Debora

Hi Debora,

Your blanking window configuration seems to be correct except for one advisory we have in SysConfig:

Based on this advisory, your blanking window should actually start 4 cycles before TBPRD. If you update your blanking window to start at TBPRD-4 do you still see the issue?

Thank you,

Luke

Hi Luke,

thank you for your reply! Today I am out of office and I cannot try what you tell me.

Tomorrow I will be in the office, I will try and I will tell you a response.

Thank you a lot!

Best regards,

Debora

Hi Luke,

this morning I tested my FW with your suggestion but the issue isn't solved. Below I show you the behavior of my system with blanking window offset set to TBPRD-4.

1) When my input is 0V, the DC of PWM7A starts correctly to 20%DC as shown in the images below:

2) When the input is between 0.03V and 0,5V the DC stay at 78%, as shown in the image below:

3) When the input is between 0.056V and 3.3V the behavior is correct, in fact the DC starts from 20% and arrived to 80%, as shown in the images below:

I have a strange behavior from 0.03V to 0.05V. How can I fix this issue?

I attached my PWM configuration and also my CMPSS configuration.

void InitEpwm7()
{
    // Disable the ePWM time base clock before configuring the module
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    EPWM_setEmulationMode(EPWM7_BASE, EPWM_EMULATION_FREE_RUN);

    //-------------------------------------------------------------------------------------------------------------------------------- SET EPWM PARAMETERS
    //EPWM with frequency of 100Khz and DC = 80%
    EPWM_setClockPrescaler(EPWM7_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBaseCounterMode(EPWM7_BASE, EPWM_COUNTER_MODE_UP);
    EPWM_setTimeBaseCounter(EPWM7_BASE, 0);
    EPWM_setTimeBasePeriod(EPWM7_BASE, TBPRD_PWM7);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A, 799);

    //-------------------------------------------------------------------------------------------------------------------------------- ENABLE ADC Trigger
    EPWM_enableADCTrigger(EPWM7_BASE, EPWM_SOC_A);
    EPWM_setADCTriggerSource(EPWM7_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPA);
    EPWM_setADCTriggerEventPrescale(EPWM7_BASE, EPWM_SOC_A, 1);

    //-------------------------------------------------------------------------------------------------------------------------------- X BAR CONFIGURATION
    // Configure TRIP4 to be CTRIP1H using the ePWM X-BAR --> CMPSS1.CTRIPH as TRIP4 input
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00);                                           //disable old mux configuration
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
    XBAR_invertEPWMSignal(XBAR_TRIP4, false);

    //-------------------------------------------------------------------------------------------------------------------------------- DEAD BAND CONFIGURATION
    //Use EPWMA as the input for both RED and FED
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    //Set the RED and FED values
    EPWM_setFallingEdgeDelayCount(EPWM7_BASE, 15);                                  //dead band = 150ns --> DBFED = FED/Ttbclk = 150ns/(1/100MHz)
    EPWM_setRisingEdgeDelayCount(EPWM7_BASE, 15);                                   //dead band = 150ns --> DBRED = RED/Ttbclk = 150ns/(1/100MHz)
    //Invert only the falling edge delayed output (AHC = Active High Complementary)
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
    //Using the delayed signals instead of the original signals
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_FED, true);
    //Do not switch output A with output B
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_B, false);

    //-------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

    //-------------------------------------------------------------------------------------------------------------------------------- SET TRIP ZONE
#define BLANKING_WINDOW
#ifdef BLANKING_WINDOW
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE);
    EPWM_setActionQualifierT1TriggerSource(EPWM7_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);

    EPWM_setDigitalCompareFilterInput(EPWM7_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT2);
    EPWM_setDigitalCompareBlankingEvent(EPWM7_BASE, EPWM_DC_WINDOW_START_TBCTR_ZERO);
    EPWM_setDigitalCompareWindowOffset(EPWM7_BASE, TBPRD_PWM7-4);
    EPWM_setDigitalCompareWindowLength(EPWM7_BASE, 199);
    EPWM_enableDigitalCompareBlankingWindow(EPWM7_BASE);
#else
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE);
    EPWM_setActionQualifierT1TriggerSource(EPWM7_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
#endif
}


void InitCmpss()
{
    EALLOW;

    //Enable the CMPSS module
    CMPSS_enableModule(CMPSS1_BASE);
    DEVICE_DELAY_US(500);

    //The High comparator negative input come from DAC
    CMPSS_configHighComparator(CMPSS1_BASE, CMPSS_INSRC_DAC);
    //The Low comparator negative input come from DAC
    CMPSS_configLowComparator(CMPSS1_BASE, CMPSS_INSRC_DAC);

    //Select input pin for CMPSS
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1, 0U);  //Select the value for CMPHP --> CMP1_HP0 = pin A2
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1, 0U);  //Select the value for CMPLP --> CMP1_LP0 = pin A2

#ifdef RAMPA
    CMPSS_configDAC(CMPSS1_BASE, (CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_RAMP));
#else
    // Sets the configuration for the internal comparator DACs.
    CMPSS_configDAC(CMPSS1_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW));
#endif

    // Sets the value of the internal DAC of the high comparator
    CMPSS_setDACValueHigh(CMPSS1_BASE, (3.3 * 4095)/3.3 );   //Set DACVALA value --> DACVALA = (DACOUT * 4095)/3.3
    // Sets the value of the internal DAC of the low comparator.
    CMPSS_setDACValueLow(CMPSS1_BASE,0U);

    //--------------------------------------------------------------------------------------------------------------------- DIGITAL FILTER CONFIGURATION
    //  Configures the digital filter of the high comparator.
    //CLKPRESCALE = 1 --> After2 sysclk the value is insert in the FIFO --> ClockPrescale = 1 + 1 = 2
    //SAMPWIN     = 9 --> Sample Windown = 9 + 1 = 10
    //THRESH      = 5 --> Threshold = 5 + 1 = 6
    CMPSS_configFilterHigh(CMPSS1_BASE, 1U, 9U, 5U);
    // Configures the digital filter of the low comparator. --> not used because we used only the CMPSS_H
    //CMPSS_configFilterLow(CMPSS1_BASE, 0U, 1U, 1U);
    CMPSS_initFilterHigh(CMPSS1_BASE);
    CMPSS_configOutputsHigh(CMPSS1_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));

    // Sets the comparator hysteresis settings.
    CMPSS_setHysteresis(CMPSS1_BASE,0U);

#ifdef RAMPA
    //maxRampVal = 1V = dacvala
    //CMPSS_configRamp(CMPSS1_BASE,19860U,20U,0U,7U,true);
    CMPSS_configRamp(CMPSS1_BASE, (3.3*65535)/3.3,20U,0U,7U,true);
#else
    // Configures the comparator subsystem's ramp generator.
    CMPSS_configRamp(CMPSS1_BASE,0U,0U,0U,1U,true);
#endif
    // Disables reset of HIGH comparator digital filter output latch on PWMSYNC
    CMPSS_disableLatchResetOnPWMSYNCHigh(CMPSS1_BASE);

    // Disables reset of LOW comparator digital filter output latch on PWMSYNC
    //CMPSS_disableLatchResetOnPWMSYNCLow(CMPSS1_BASE);

    // Sets the ePWM module blanking signal that holds trip in reset.
    CMPSS_configBlanking(CMPSS1_BASE,1U);
    // Disables an ePWM blanking signal from holding trip in reset.
    CMPSS_enableBlanking(CMPSS1_BASE);


    if((HWREGH(CMPSS1_BASE + CMPSS_O_COMPSTSCLR) & CMPSS_COMPSTSCLR_LSYNCCLREN) == 0)
    {
        CMPSS_configLatchOnPWMSYNC(CMPSS1_BASE, true, false);
    }
    else
    {
        CMPSS_configLatchOnPWMSYNC(CMPSS1_BASE, true, true);
    }


    XBAR_setOutputLatchMode(OUTPUTXBAR_BASE, XBAR_OUTPUT7, false);
    XBAR_invertOutputSignal(OUTPUTXBAR_BASE, XBAR_OUTPUT7, false);

    XBAR_setOutputMuxConfig(OUTPUTXBAR_BASE, XBAR_OUTPUT7, XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH);
    XBAR_enableOutputMux(OUTPUTXBAR_BASE, XBAR_OUTPUT7, XBAR_MUX00);

    EDIS;
}

Please, help me to solve the issue. We need to have a minimum DutyCycle.

The channels of the oscilloscope are:

• CH2 = EPWM7A
• CH3 = CTRIP OUT 
• CH4 = EPWM7B

Thank you in advance,

Best regards,

Debora

Hi Debora,

In these cases, what is your CMPSS reference DAC value set to? If the sensed inductor current is close to the threshold value you have set in CMPSS, you may see glitches as CTRIPH toggles between high to low (result of noise on the analog reading). This normally should not be a concern in normal operation as your inductor current slews, but you may see it in static testing. Is your PCMC working in normal operation? Also, which of your pictures corresponds to this edge condition between 30 and 50mV?

Regards,
Peter

Hi Peter,

thank you for the reply. 

My PCMC works in normal operation. The DAC reference is the ramp value calculated cycle by cycle and set thank to the functions CMPSS_setMaxRampValue(CMPSS1_BASE, maxRampValue); and CMPSS_setRampDecValue(CMPSS1_BASE, decrementValue);

This is my configuration:

Between 30mV and 50mV the image is this:

Between 30mV and 50mV I have the maximum duty cycle.

Thank you for the help.

best regards,

Debora

Hi Debora,

Thanks for your scope shots. Since it looks like this issue is affecting your closed loop operation, it may be a little bit harder to evaluate. My initial suspicion is that at 30 mV and 50 mV the sensed inductor current is not able to reach the configured CMPSS DAC reference value to shut off the PWMs in time, so your PWMs default to max duty cycle. Is there anyway you can log the value of the DAC that occurs at this voltage range? Are you clamping the output of your control effort? Please ensure that calculated CMPSS reference DAC is properly clamped per your systems characteristics.

Regards,

Peter

Hi Peter,

thank you for the reply. 

We are running the system in an open loop giving the voltage input (A2) through a potentiometer without driving any power supply.

Thanks to your comment, I found an error on my code! but unfortunately, I am not able to solve it! In fact, to calculate the maxRampValu and the decrementVal I need to know the actual duty cycle of my EPWM. To read the actual duty cycle, I use the function EPWM_getCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A); but this function give me always the configured value of CMPA = 799, so I am not reading the current DC value! With my LAUNCHXL-F2800137 and with C2000ware, how I can read the actual duty cycle?

How I can read the current duty cycle of my EPWM?

Thank you.

Best Regards,

Debora

Hi Debora,

In the EPWM module, we have a DCCAP digital compare capture module that captures the TBCTR reading at the point that digital compare event occurs, you should be able to leverage this register to calculate the actual duty of the PWM pulse. You can also choose to use an eCAP module to capture the duty of the pulse

Regards,

Peter

Hi Peter,

thank you for your reply. I configured the eCAP module and now I am able to read in the right way the duty cycle of my ePWM module.

In my FW, now I have 2 interrupts: one is for the ADC acquisitions and one is for the eCAP module. But when the interrupt of eCAP module is enabled, my FW doesn't go in the ISR of ADCInterrupt, never. If I disabled the interrupt of eCAP, the interrupt of the ADC is working.

I thought I had problems with interrupt priorities as shown in the image reported below:

But it can be impossible due to this part of my TRM:

How I can solve the issue? 

I attached the configurations of my ADC and eCAP module for more details:

void InitEcap()
{
    dutyCycle = 0;

    // Disable ,clear all capture flags and interrupts
    ECAP_disableInterrupt(ECAP1_BASE, (ECAP_ISR_SOURCE_CAPTURE_EVENT_1  |
                                       ECAP_ISR_SOURCE_CAPTURE_EVENT_2  |
                                       ECAP_ISR_SOURCE_CAPTURE_EVENT_3  |
                                       ECAP_ISR_SOURCE_CAPTURE_EVENT_4  |
                                       ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                                       ECAP_ISR_SOURCE_COUNTER_PERIOD   |
                                       ECAP_ISR_SOURCE_COUNTER_COMPARE));
    ECAP_clearInterrupt(ECAP1_BASE,   (ECAP_ISR_SOURCE_CAPTURE_EVENT_1  |
                                       ECAP_ISR_SOURCE_CAPTURE_EVENT_2  |
                                       ECAP_ISR_SOURCE_CAPTURE_EVENT_3  |
                                       ECAP_ISR_SOURCE_CAPTURE_EVENT_4  |
                                       ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                                       ECAP_ISR_SOURCE_COUNTER_PERIOD   |
                                       ECAP_ISR_SOURCE_COUNTER_COMPARE));

    // Disables time stamp capture.
    ECAP_disableTimeStampCapture(ECAP1_BASE);
    // Stops Time stamp counter.
    ECAP_stopCounter(ECAP1_BASE);
    // Sets eCAP in Capture mode.
    ECAP_enableCaptureMode(ECAP1_BASE);
    // Sets the capture mode.
    ECAP_setCaptureMode(ECAP1_BASE,ECAP_CONTINUOUS_CAPTURE_MODE,ECAP_EVENT_4);
    // Sets the Capture event prescaler.
    ECAP_setEventPrescaler(ECAP1_BASE, 0U);
    // Sets the Capture event polarity.
    ECAP_setEventPolarity(ECAP1_BASE,ECAP_EVENT_1,ECAP_EVNT_RISING_EDGE);
    ECAP_setEventPolarity(ECAP1_BASE,ECAP_EVENT_2,ECAP_EVNT_FALLING_EDGE);
    ECAP_setEventPolarity(ECAP1_BASE,ECAP_EVENT_3,ECAP_EVNT_RISING_EDGE);
    ECAP_setEventPolarity(ECAP1_BASE,ECAP_EVENT_4,ECAP_EVNT_FALLING_EDGE);
    // Configure counter reset on events
    ECAP_enableCounterResetOnEvent(ECAP1_BASE,ECAP_EVENT_1);
    ECAP_enableCounterResetOnEvent(ECAP1_BASE,ECAP_EVENT_2);
    ECAP_enableCounterResetOnEvent(ECAP1_BASE,ECAP_EVENT_3);
    ECAP_enableCounterResetOnEvent(ECAP1_BASE,ECAP_EVENT_4);
    // Select eCAP input.
    ECAP_selectECAPInput(ECAP1_BASE,ECAP_INPUT_INPUTXBAR7);
    // Sets a phase shift value count.
    ECAP_setPhaseShiftCount(ECAP1_BASE,0U);
    // Enable counter loading with phase shift value.
    ECAP_enableLoadCounter(ECAP1_BASE);
    // Configures Sync out signal mode.
    ECAP_setSyncOutMode(ECAP1_BASE,ECAP_SYNC_OUT_SYNCI);
    // Set up the source for sync-in pulse..
    ECAP_setSyncInPulseSource(ECAP1_BASE,ECAP_SYNC_IN_PULSE_SRC_DISABLE);
    // Starts Time stamp counter for myECAP0.
    ECAP_startCounter(ECAP1_BASE);
    // Enables time stamp capture for myECAP0.
    ECAP_enableTimeStampCapture(ECAP1_BASE);
    // Re-arms the eCAP module for myECAP0.
    ECAP_reArm(ECAP1_BASE);
    // Enables interrupt source for myECAP0.
    ECAP_enableInterrupt(ECAP1_BASE,(ECAP_ISR_SOURCE_CAPTURE_EVENT_4));
    Interrupt_register(INT_ECAP1, &ECAPInterrupt);
    Interrupt_enable(INT_ECAP1);
}

void InitAdc()
{
    // Setup VREF as internal
    ADC_setVREF(ADCA_BASE, ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);

    // Set ADCCLK divider to /1
    ADC_setPrescaler(ADCA_BASE, ADC_CLK_DIV_1_0);

    // Set pulse positions to late
    ADC_setInterruptPulseMode(ADCA_BASE, ADC_PULSE_END_OF_CONV);

    //SOC0 will convert A0 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN0, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER0);

    //SOC1 will convert A1 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN1, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1);

    //SOC2 will convert A2 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN2, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER2);

    //SOC3 will convert A3 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER3, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN3, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER3);

    //SOC4 will convert A4 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER4, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN4, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER4);

    //SOC5 will convert A5 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER5, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN5, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER5);

    //SOC6 will convert A6 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER6, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN6, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER6);

    ADC_enableInterrupt(ADCA_BASE, ADC_INT_NUMBER1);

    Interrupt_enable(INT_ADCA1);

    Interrupt_register(INT_ADCA1, &ADCInterrupt);

    ADC_enableConverter(ADCA_BASE);

    DEVICE_DELAY_US(1000);

    // IIR Filter Initialization
    iir.dbuffer_ptr = dbuffer;
    iir.coeff_ptr = (long*) coeff;
    iir.qfmat = IIR32_LPF_QFMAT;
    iir.nbiq = IIR32_LPF_NBIQ;
    iir.isf = IIR32_LPF_ISF;
    iir.init(&iir);
}

Thank you in advance.

Best Regards,

Debora

Hi Debora,

Are you correctly acknowledging your interrupts at the end of the ISR as well as clearing any necessary peripheral interrupt registers? And what frequency are your interrupts operating at? One point could also be that your ISR is taking too long or your ECAP ISR is blocking the CPU the entire time. Can you send your ISR?

Regards,
Peter

Hi Peter,

Thank you for your reply.

Thanks to your suggestion, I found that the ISR of ADC causes an ADC interrupt overflow and the ISR of ECAP is slowly. So I clear the interrupt flag of ADC in the ISR of eCAP and the program running correctly without errors. In this case the ISR of ADC is lost some times but ADC ISR can still be servered properly.

Now I attached my ISRs:

interrupt void ADCInterrupt()
{
     //-------------------------- Check interrupt overflow -------------------------
     //Check if an overflow has occurred
     if( ADC_getInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1) == true )
     {
     ADC_clearInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1);
     ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
     }
     //-----------------------------------------------------------------------------

     //Leggo i 6 ingressi dell'ADC
     bchrgVariable.VoutN_BB = (ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER0)); //A0
     bchrgVariable.VoutP_BB = (ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER1)); //A1
     bchrgVariable.BB_I_FB = (ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER2)); //A2
     bchrgVariable.VinP = (ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER3)); //A3
     bchrgVariable.VinN = (ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER4)); //A4
     bchrgVariable.V_CAP_P = (ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER5)); //A5
     bchrgVariable.V_CAP_N = (ADC_readResult(ADCARESULT_BASE, ADC_SOC_NUMBER6)); //A6

     //Calcolo le tensioni totali
     bchrgVariable.vIn = bchrgVariable.VinP - bchrgVariable.VinN;
     bchrgVariable.vOut = bchrgVariable.VoutP_BB - bchrgVariable.VoutN_BB;
     bchrgVariable.vBus = bchrgVariable.V_CAP_P - bchrgVariable.V_CAP_N;

     //Calcolo l'errore e lo do in pasto al filtro
     int32_t error = 3102 - bchrgVariable.vOut;
     iir.input = error;
     iir.calc(&iir);
     int32_t outputFilter = iir.output32;

     //Calcolo Iref in funzione di K
     float32_t Iref = K * outputFilter;

     period = cap1Count + cap2Count;
     dutyCycle = (float32_t)cap1Count/(float32_t)period;

     //Calcolo la VPP che serve per impostare il valore della rampa
     float32_t VPP = - ((0.18f - dutyCycle) * Ri * Ts * Iref)/Lo;
     maxRampValue = VPP * ((4096-1)/3.3); //uint16_t
     decrementValue = maxRampValue * ((float32_t)Fs/(float32_t)Fclk); //uint16_t

     //Setto i nuovi valori per la rampa e per il decrementVal della rampa
     CMPSS_setMaxRampValue(CMPSS1_BASE, maxRampValue);
     CMPSS_setRampDecValue(CMPSS1_BASE, decrementValue);

     //Reset the ADCInterrupt flag in the ISR of ECAP.
}

interrupt void ECAPInterrupt()
{
     cap1Count = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_1);
     cap2Count = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_2);
     cap3Count = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_3);
     cap4Count = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_4);

     ECAP_reArm(ECAP1_BASE);

     // Clear interrupt flags for more interrupts.
     ECAP_clearInterrupt(ECAP1_BASE,ECAP_ISR_SOURCE_CAPTURE_EVENT_2);
     ECAP_clearGlobalInterrupt(ECAP1_BASE);

     // Acknowledge the group interrupt for more interrupts.
     Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP4);

     //Clear the interrupt flag
     ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
     Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}

Sorry if I don't use the Insert/Code instruction but it still to give me this error:

Thank you in advance.

Best Regards,

Debora

Hi Peter,

I have another question: I implemented a peak current mode with duty cycle limited (between 20 % and 80%). But now I want that when the duty cycle stays at 20% for a certain time, the EPWMxA is set to 0 and the EPWMxB is set to 1. How I can configure that?

I attached my ePWM confiugration below:

void InitEpwm7()
{
    // Disable the ePWM time base clock before configuring the module
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    EPWM_setEmulationMode(EPWM7_BASE, EPWM_EMULATION_FREE_RUN);

    //-------------------------------------------------------------------------------------------------------------------------------- SET EPWM PARAMETERS
    //EPWM with frequency of 100Khz and DC = 80%
    EPWM_setClockPrescaler(EPWM7_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBaseCounterMode(EPWM7_BASE, EPWM_COUNTER_MODE_UP);
    EPWM_setTimeBaseCounter(EPWM7_BASE, 0);
    EPWM_setTimeBasePeriod(EPWM7_BASE, TBPRD_PWM7);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A, 799);

    //-------------------------------------------------------------------------------------------------------------------------------- ENABLE ADC Trigger
    EPWM_enableADCTrigger(EPWM7_BASE, EPWM_SOC_A);
    EPWM_setADCTriggerSource(EPWM7_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_PERIOD);
    EPWM_setADCTriggerEventPrescale(EPWM7_BASE, EPWM_SOC_A, 1);

    //-------------------------------------------------------------------------------------------------------------------------------- X BAR CONFIGURATION
    // Configure TRIP4 to be CTRIP1H using the ePWM X-BAR --> CMPSS1.CTRIPH as TRIP4 input
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00);                                           //disable old mux configuration
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
    XBAR_invertEPWMSignal(XBAR_TRIP4, false);

    //-------------------------------------------------------------------------------------------------------------------------------- DEAD BAND CONFIGURATION
    //Use EPWMA as the input for both RED and FED
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    //Set the RED and FED values
    EPWM_setFallingEdgeDelayCount(EPWM7_BASE, 15);                                  //dead band = 150ns --> DBFED = FED/Ttbclk = 150ns/(1/100MHz)
    EPWM_setRisingEdgeDelayCount(EPWM7_BASE, 15);                                   //dead band = 150ns --> DBRED = RED/Ttbclk = 150ns/(1/100MHz)
    //Invert only the falling edge delayed output (AHC = Active High Complementary)
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
    //Using the delayed signals instead of the original signals
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_FED, true);
    //Do not switch output A with output B
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_B, false);

    //-------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

    //-------------------------------------------------------------------------------------------------------------------------------- SET TRIP ZONE
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE);
    EPWM_setActionQualifierT1TriggerSource(EPWM7_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);

    //-------------------------------------------------------------------------------------------------------------------------------- SET BLANKING WINDOW
    EPWM_setDigitalCompareFilterInput(EPWM7_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT2);
    EPWM_setDigitalCompareBlankingEvent(EPWM7_BASE, EPWM_DC_WINDOW_START_TBCTR_ZERO);
    EPWM_setDigitalCompareWindowOffset(EPWM7_BASE, TBPRD_PWM7-4);
    EPWM_setDigitalCompareWindowLength(EPWM7_BASE, 199);
    EPWM_enableDigitalCompareBlankingWindow(EPWM7_BASE);
}

Thank you.

Best Regards,

Debora

Hi Debora,

Let me loop in an interrupt expert to assist your first question, but glad that you can at least see both interrupts now.

For the second question, I don't believe we would have any feature like this in the hardware of the EPWM module. You would need to add a software-based implementation. Something you could do could be to add a counter variable into your project and in your ECAP ISR, to record the duty of the pulse and if it causes this 20% minimum duty condition, you can increment a counter. Once that counter reaches a certain threshold, you can choose to use a Action Qualifier continuous software force (EPWM_setActionQualifierContSWForceAction()) in order to set the EPWMs to a defined state.

Regards,

Peter

Hi Peter,

thank you for your reply. Your suggestion is good! Today, I tried to apply what do you suggested to me and it works. But I have found another issue! In fact, I have a timer1 interrupt that works as heart bit and it stops to work when I connect EPWM7A to input xbar 7 which is the GPIO of eCAP. When I disconnect input xbar 7 from ePWM7A, the timer1 interrupt returns to work fine. 

How I can solve the issue? Why this issue is generated?

Timer 1 doesn't work with epwm, with adc and with eCap, so I don't know what appens! Why when I connect the ePWM7A with eCAP, timer1 stop working? And when I disconnect the ePWM7A from eCap, timer1 resturn to working?

In the future I need to have timer1 interrupt for my application, so it cannot be not work.

I attached the configuration of Timer1 interrupt and also the configuration of ADC, CMPSS, EPWM:

void InitTimer1()
{

    cpuTimer1IntCount = 0;

    // ISR for the CPU timer interrupt
    Interrupt_register(INT_TIMER1, &Timer1Interrupt);

    // Initializes the Device Peripheral.
    InitCPUTimers();

    // Configure CPU-Timer 1 to interrupt every 100 ms:  1 Period respectively (in uSeconds)
    ConfigCPUTimer(CPUTIMER1_BASE, DEVICE_SYSCLK_FREQ, 100000);

    // To ensure precise timing, use write-only instructions to write to the entire register. Therefore, if any of the configuration bits are changed
    // in ConfigCPUTimer and InitCPUTimers, the below settings must also  be updated
    CPUTimer_enableInterrupt(CPUTIMER1_BASE);

    // Enables CPU int13 which is connected to CPU-Timer 1
    Interrupt_enable(INT_TIMER1);

    // Starts CPU-Timer 1
    CPUTimer_startTimer(CPUTIMER1_BASE);

    EINT;
    ERTM;
}



//*******************************************************************************************
//          Name: InitCPUTimers
//
//   Description: This function initializes the CPU timer to a know state
//*******************************************************************************************
void InitCPUTimers(void)
{
    // Initialize timer period to maximum
    CPUTimer_setPeriod(CPUTIMER1_BASE, 0xFFFFFFFF);

    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
    CPUTimer_setPreScaler(CPUTIMER1_BASE, 0);

    // Make sure timer is stopped
    CPUTimer_stopTimer(CPUTIMER1_BASE);

    // Reload all counter register with period value
    CPUTimer_reloadTimerCounter(CPUTIMER1_BASE);

    // Reset interrupt counter
    cpuTimer1IntCount = 0;
}



//*******************************************************************************************
//          Name: ConfigCPUTimer
//
//   Description: This function initializes the selected timer to the period specified by the
//                "freq" and "period" parameters. The "freq" is entered as Hz and the period
//                in uSeconds. The timer is held in the stopped state after configuration.
//*******************************************************************************************
void ConfigCPUTimer(uint32_t cpuTimer, float freq, float period)
{
    uint32_t temp;

    // Initialize timer period:
    temp = (uint32_t)((freq / 1000000) * period);
    CPUTimer_setPeriod(cpuTimer, temp);

    // Set pre-scale counter to divide by 1 (SYSCLKOUT):
    CPUTimer_setPreScaler(cpuTimer, 0);

    // Initializes timer control register. The timer is stopped, reloaded, free run disabled,
    // and interrupt enabled. Additionally, the free and soft bits are set
    CPUTimer_stopTimer(cpuTimer);
    CPUTimer_reloadTimerCounter(cpuTimer);
    CPUTimer_setEmulationMode(cpuTimer, CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
    CPUTimer_enableInterrupt(cpuTimer);

    if(cpuTimer == CPUTIMER1_BASE)
    {
        cpuTimer1IntCount = 0;
    }
}

void InitAdc()
{
    // Setup VREF as internal
    ADC_setVREF(ADCA_BASE, ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);

    // Set ADCCLK divider to /1
    ADC_setPrescaler(ADCA_BASE, ADC_CLK_DIV_1_0);

    // Set pulse positions to late
    ADC_setInterruptPulseMode(ADCA_BASE, ADC_PULSE_END_OF_CONV);

    //SOC0 will convert A0 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN0, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER0);

    //SOC1 will convert A1 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN1, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER1);

    //SOC2 will convert A2 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN2, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER2);

    //SOC3 will convert A3 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER3, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN3, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER3);

    //SOC4 will convert A4 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER4, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN4, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER4);

    //SOC5 will convert A5 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER5, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN5, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER5);

    //SOC6 will convert A6 pin
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER6, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN6, 10);
    ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER6);

    ADC_enableInterrupt(ADCA_BASE, ADC_INT_NUMBER1);

    Interrupt_enable(INT_ADCA1);

    Interrupt_register(INT_ADCA1, &ADCInterrupt);

    ADC_enableConverter(ADCA_BASE);

    DEVICE_DELAY_US(1000);

    // IIR Filter Initialization
    iir.dbuffer_ptr = dbuffer;
    iir.coeff_ptr = (long*) coeff;
    iir.qfmat = IIR32_LPF_QFMAT;
    iir.nbiq = IIR32_LPF_NBIQ;
    iir.isf = IIR32_LPF_ISF;
    iir.init(&iir);
}


void InitCmpss()
{
    EALLOW;

    //Enable the CMPSS module
    CMPSS_enableModule(CMPSS1_BASE);
    DEVICE_DELAY_US(500);

    //The High comparator negative input come from DAC
    CMPSS_configHighComparator(CMPSS1_BASE, CMPSS_INSRC_DAC);
    //The Low comparator negative input come from DAC
    CMPSS_configLowComparator(CMPSS1_BASE, CMPSS_INSRC_DAC);

    //Select input pin for CMPSS
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1, 0U);  //Select the value for CMPHP --> CMP1_HP0 = pin A2
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1, 0U);  //Select the value for CMPLP --> CMP1_LP0 = pin A2

#ifdef RAMPA
    CMPSS_configDAC(CMPSS1_BASE, (CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_RAMP));
#else
    // Sets the configuration for the internal comparator DACs.
    CMPSS_configDAC(CMPSS1_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW));
#endif

    // Sets the value of the internal DAC of the high comparator
    CMPSS_setDACValueHigh(CMPSS1_BASE, (3.3 * 4095)/3.3 );   //Set DACVALA value --> DACVALA = (DACOUT * 4095)/3.3
    // Sets the value of the internal DAC of the low comparator.
    CMPSS_setDACValueLow(CMPSS1_BASE,0U);

    //--------------------------------------------------------------------------------------------------------------------- DIGITAL FILTER CONFIGURATION
    //  Configures the digital filter of the high comparator.
    //CLKPRESCALE = 1 --> After2 sysclk the value is insert in the FIFO --> ClockPrescale = 1 + 1 = 2
    //SAMPWIN     = 9 --> Sample Windown = 9 + 1 = 10
    //THRESH      = 5 --> Threshold = 5 + 1 = 6
    CMPSS_configFilterHigh(CMPSS1_BASE, 1U, 9U, 5U);
    // Configures the digital filter of the low comparator. --> not used because we used only the CMPSS_H
    //CMPSS_configFilterLow(CMPSS1_BASE, 0U, 1U, 1U);
    CMPSS_initFilterHigh(CMPSS1_BASE);
    CMPSS_configOutputsHigh(CMPSS1_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));

    // Sets the comparator hysteresis settings.
    CMPSS_setHysteresis(CMPSS1_BASE,0U);

#ifdef RAMPA
    //maxRampVal = 1V = dacvala
    //CMPSS_configRamp(CMPSS1_BASE,19860U,20U,0U,7U,true);
    CMPSS_configRamp(CMPSS1_BASE, (3.3*65535)/3.3,20U,0U,7U,true);
#else
    // Configures the comparator subsystem's ramp generator.
    CMPSS_configRamp(CMPSS1_BASE,0U,0U,0U,1U,true);
#endif
    // Disables reset of HIGH comparator digital filter output latch on PWMSYNC
    CMPSS_disableLatchResetOnPWMSYNCHigh(CMPSS1_BASE);

    // Disables reset of LOW comparator digital filter output latch on PWMSYNC
    //CMPSS_disableLatchResetOnPWMSYNCLow(CMPSS1_BASE);

    // Sets the ePWM module blanking signal that holds trip in reset.
    CMPSS_configBlanking(CMPSS1_BASE,1U);
    // Disables an ePWM blanking signal from holding trip in reset.
    CMPSS_enableBlanking(CMPSS1_BASE);


    if((HWREGH(CMPSS1_BASE + CMPSS_O_COMPSTSCLR) & CMPSS_COMPSTSCLR_LSYNCCLREN) == 0)
    {
        CMPSS_configLatchOnPWMSYNC(CMPSS1_BASE, true, false);
    }
    else
    {
        CMPSS_configLatchOnPWMSYNC(CMPSS1_BASE, true, true);
    }


    XBAR_setOutputLatchMode(OUTPUTXBAR_BASE, XBAR_OUTPUT7, false);
    XBAR_invertOutputSignal(OUTPUTXBAR_BASE, XBAR_OUTPUT7, false);

    XBAR_setOutputMuxConfig(OUTPUTXBAR_BASE, XBAR_OUTPUT7, XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH);
    XBAR_enableOutputMux(OUTPUTXBAR_BASE, XBAR_OUTPUT7, XBAR_MUX00);

    EDIS;
}


void InitEpwm7()
{
    // Disable the ePWM time base clock before configuring the module
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    EPWM_setEmulationMode(EPWM7_BASE, EPWM_EMULATION_FREE_RUN);

    //-------------------------------------------------------------------------------------------------------------------------------- SET EPWM PARAMETERS
    //EPWM with frequency of 100Khz and DC = 80%
    EPWM_setClockPrescaler(EPWM7_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBaseCounterMode(EPWM7_BASE, EPWM_COUNTER_MODE_UP);
    EPWM_setTimeBaseCounter(EPWM7_BASE, 0);
    EPWM_setTimeBasePeriod(EPWM7_BASE, TBPRD_PWM7);
    EPWM_setCounterCompareValue(EPWM7_BASE, EPWM_COUNTER_COMPARE_A, 799);

    //-------------------------------------------------------------------------------------------------------------------------------- ENABLE ADC Trigger
    EPWM_enableADCTrigger(EPWM7_BASE, EPWM_SOC_A);
    EPWM_setADCTriggerSource(EPWM7_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_PERIOD);
    EPWM_setADCTriggerEventPrescale(EPWM7_BASE, EPWM_SOC_A, 1);

    //-------------------------------------------------------------------------------------------------------------------------------- X BAR CONFIGURATION
    // Configure TRIP4 to be CTRIP1H using the ePWM X-BAR --> CMPSS1.CTRIPH as TRIP4 input
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00);                                           //disable old mux configuration
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
    XBAR_invertEPWMSignal(XBAR_TRIP4, false);

    //-------------------------------------------------------------------------------------------------------------------------------- DEAD BAND CONFIGURATION
    //Use EPWMA as the input for both RED and FED
    EPWM_setRisingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    EPWM_setFallingEdgeDeadBandDelayInput(EPWM7_BASE, EPWM_DB_INPUT_EPWMA);
    //Set the RED and FED values
    EPWM_setFallingEdgeDelayCount(EPWM7_BASE, 15);                                  //dead band = 150ns --> DBFED = FED/Ttbclk = 150ns/(1/100MHz)
    EPWM_setRisingEdgeDelayCount(EPWM7_BASE, 15);                                   //dead band = 150ns --> DBRED = RED/Ttbclk = 150ns/(1/100MHz)
    //Invert only the falling edge delayed output (AHC = Active High Complementary)
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
    EPWM_setDeadBandDelayPolarity(EPWM7_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
    //Using the delayed signals instead of the original signals
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_RED, true);
    EPWM_setDeadBandDelayMode(EPWM7_BASE, EPWM_DB_FED, true);
    //Do not switch output A with output B
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_A, false);
    EPWM_setDeadBandOutputSwapMode(EPWM7_BASE, EPWM_DB_OUTPUT_B, false);

    //-------------------------------------------------------------------------------------------------------------------------------- SET ACTION QUALIFIER
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

    //-------------------------------------------------------------------------------------------------------------------------------- SET TRIP ZONE
    EPWM_selectDigitalCompareTripInput(EPWM7_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
    EPWM_setTripZoneDigitalCompareEventCondition(EPWM7_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneAction(EPWM7_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE);
    EPWM_setActionQualifierT1TriggerSource(EPWM7_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);
    EPWM_setActionQualifierAction(EPWM7_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);

    EPWM_setDigitalCompareFilterInput(EPWM7_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT2);
    EPWM_setDigitalCompareBlankingEvent(EPWM7_BASE, EPWM_DC_WINDOW_START_TBCTR_ZERO);
    EPWM_setDigitalCompareWindowOffset(EPWM7_BASE, TBPRD_PWM7-4);
    EPWM_setDigitalCompareWindowLength(EPWM7_BASE, 99);
    EPWM_enableDigitalCompareBlankingWindow(EPWM7_BASE);
}

Please help me to solve also this issue.

Thank you in advance.

Best Regards,

Debora

Hi Debora,

Does this happen with all XBARs or just XBAR7? Can you try choosing a different XBAR, since the device has multiple? The ECAP should be able to accept inputs from any of the XBARs so the issue may just be with the one that you are currently using

Regards,

Peter

Hi Peter,

thank you for the reply. I tried with another XBAR pin but the behavior is the same. I tried also with a new lauch pad and also in this case the behavior is the same. I don't know how I can do to solve this issue.

Please help me.

Thank you.

Best Regards,

Debora

Hi Debora,

I discussed this with our eCAP expert and they don't believe this issue is resulting from the eCAP itself. Allow me to consult with our XBAR and CPUTimer experts to see which may be causing this issue.

Regards,

Peter

Hi Peter,

Thank you for the reply.

Ok, I wait your reply after your consultation with XBAR and CPUTImer experts.

Thank you very much.

Best Regards,

Debora