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TMS320F280039C-Q1: C2000 microcontrollers forum

Huihuang Chen
Expert 4010 points
Part Number: TMS320F280039C-Q1

Tool/software:

Hi Champ,

From the datasheet, when use internal VREG, the Cvdd  total should 10-26.8uF.

How to understand the maximum 26.8uF value limitation ?

If over 26.8uF, what is the failure mode?

  • 0
    TI__Mastermind 19050 points

    Hi Huihuang

    Please see our hardware design guide section 3.4.1 Power Requirements for context on decoupling capacitors: https://www.ti.com/lit/an/spracz9a/spracz9a.pdf. 

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Expert 4010 points

    Hi Allison,

    I don't think you answered  my question!

    You didn't provide the failure mode over 26.8uF case.

    If you are not right person, please help involve the expert on this question!

    Thanks!

  • 0 in reply to Huihuang Chen
    TI__Mastermind 19050 points

    Hi Huihuang,

    The point of having the decoupling capacitance is to help control/smooth voltage spikes/drops in the power supply. But if you are using a higher capacitance, the rise time of the LDO may be slower. This could, for example, affect the device upon reset depending on the timing of when XRSn is released, so the result could put the device out of spec. The datasheet PMM section has more details on the power on timings and diagrams of the ramp ups.

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Expert 4010 points

    Hi Allison,

    Could you more specific which timing will be affect?

    Please list all the timing which will be affect by  over 26.8uF case.

    Thanks!

  • 0 in reply to Huihuang Chen
    TI__Genius 11335 points

    Hi Huihuang,

    Allison is currently out of office until Tuesday 7/9 so please expect some delay in her response.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Guru* 76420 points

    Huihuang,

    As we increase the capacitance on the VDD supply we will also increase the time it takes for the internal LDO to fully ramp the 1.2V supply when it turns on.  The values in the DS are derived with this in mind, in relation to when the internal POR/BOR gets released based on the VDDIO supply level.  If this value is too large there may be risk that XRSn is released before the 1.2V is within the DS tolerance for this supply rail.

    If customer has already placed a larger capacitance on the VDD net, they could look at the level on a scope along with VDDIO/XRSn during power up to see if there is any risk to the above occurring.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 4010 points

    Matt,

    Can you advise which value in the DS will be affect if increase the capacitance on the VDD?

    From the datasheet , i just see tw(RSL1) be related to reset, but this timing is after VDD stable not VDDIO.

  • 0 in reply to Huihuang Chen
    TI__Guru* 76420 points

    Huihuang,

    According to the DS, the POR on VDD will release at ~1V, and then supply will have 100us to reach spec minimum of 1.14V, so extra 140mV.  Cap values published in the DS will ensure that above is met.  If customer has larger cap values there may be some risk of not being at 1.14V when XRSn releases and device running out of specification.


    Best,

    Matthew