Tool/software:
Hello TI experts,
We have a scenario where we want to receive data through SCI but the length is variable. how to address this?
And is there a way to watch FIFO data directly other than buffer.
Thanks & Regards
Raghu
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Tool/software:
Hello TI experts,
We have a scenario where we want to receive data through SCI but the length is variable. how to address this?
And is there a way to watch FIFO data directly other than buffer.
Thanks & Regards
Raghu
Hi Raghu,
By "the length is variable," do you mean that the amount of data bits in each character received are variable or that the number of characters received at a time are variable?
To answer your second question, there is no way to view the SCI FIFOs directly in the debugger since they are not contained in registers. I would suggest viewing the RX buffer and using the SCIFFRX register to see how many characters are present in the FIFO and view other FIFO status flags.
Best Regards,
Delaney
Hi Delaney,
The amount of data (no of characters) received will be vary at every reception.
Thanks & Regards
Raghu
Hi Raghu,
I see, thank you for clarifying. In this case, I believe the best option would be to set the FIFO level to whatever the highest number of bytes the lengths will be divisible by. Assuming you have odd numbered lengths, this would be a FIFO level of 1. Then you can store some different status information in global flags or buffers to keep track of where in the received message you are.
If the lengths received will be in a known order, you would be able to take a more optimized approach. You can keep track of the current FIFO level and change the trigger level after each reception to the next receptions length. If this is done in the ISR it should be able to take effect for the next ISR.
Best Regards,
Delaney
Hi Delaney,
Thanks for your response. I get data anything from 81 chars to 122 chars and it is not human readable and very unpredictable, but we cannot afford to miss any data, and I receive data periodically.
Thanks & Regards,
Raghu
Hi Raghu,
I see, yes in that case you would have to use a 1-byte (1/16) FIFO trigger level since there is no timeout interrupt on the SCI receiver. This configuration is basically the same as if you disabled the FIFO. I would suggest keeping the SCI RX ISR very short in this case and avoiding having too many other higher priority interrupts that could block the SCI RX ISR, as both of these things could cause data loss. You can also enable the RXERROR interrupt and check the error flags inside the SCI RX ISR during debugging to ensure no overrun/data loss occurs with this setup.
Best Regards,
Delaney