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TIDM-02010: TIDM-02010 TMS320F2800137 : Calculating PFC-VAC-ADC Sampling Time

Ankit Saxena
Prodigy 210 points
Part Number: TIDM-02010
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi,

According to the TIDM-02010 Schematic, the RC values for Vac are as follows:

  • Cs (Input Capacitance): 6.8 nF
  • Rs (Input Resistance): 150 Ohms


When using the Sample Time Calculator in SysConfig (with a Settling Error [LSB] of 0.5), it calculates the Sample Window as 335 SYSCLK counts, which is approximately 2790.61 ns.

However, in the code, a Sample Window of 20 is used (#define PFC_V_ADC_SAMPLE_WINDOW 20) for PFC VAC ADC.

I am having difficulty understanding the calculation behind this discrepancy. Could you please explain the reasoning behind this?

Additionally, I would appreciate it if you could help clarify the concept of Settling Error, as it is not entirely clear to me.

Thank you!

  • 0
    TI__Mastermind 43276 points

    Hi,

    Ankit Saxena said:
    I am having difficulty understanding the calculation behind this discrepancy. Could you please explain the reasoning behind this?

    The smaller Sample Window (ACQPS) allows for faster ADC sensing of the PFC VAC signal. This can allow for faster detection of the VAC input frequency (less lag), but the voltage magnitude accuracy will of course be worse. I believe Power Factor (PF) will be better with this config, but THD may be worse. You could try testing different S/H times to compare.

    Ankit Saxena said:
    Additionally, I would appreciate it if you could help clarify the concept of Settling Error, as it is not entirely clear to me.

    Settling error manifests as inaccuracies in your ADC sensing, increasing your Sample Window (ACQPS) will increase the settling time of the ADC sample-and-hold circuit. You can reference the app note below for in depth overview on ADC input circuit including settling error.

    https://www.ti.com/lit/spract6 

    Best,

    Kevin