This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280039C-Q1: Why MCAN_getRxFIFOStatus will affect EPWMx ISR?

Part Number: TMS320F280039C-Q1

Tool/software:

Hi Experts,

I am asking for my customer here.

Why MCAN_getRxFIFOStatus will affect EPWMx ISR?

MCAN_getRxFIFOStatus call during for(;;), 

CH2: EPWM interrupt enters high and exits low CH4: EPWM1 ​​drive M: Frequency trend of CH2 channel

#1.MCAN_getRxFIFOStatus call during for(;;), EPWM1 interrupt will abnormally happen.

 #2.When the customer comments the MCAN_getRxFIFOStatus() function, the problem disappears.

Any suggestion guide from your side? Thanks.

  • Hi Shaoxing,

    From the waveform, the oscope channel 4 is a PWM signal and oscope channel 2 is a GPIO signal toggled in PWM ISR. The PWM ISR is triggered at the rising edge (event CTR=Zero).

    How many interrupts enabled in your code? What happens if you change the interrupt to be generated at CMPA match? 

    Can you share your code for reproducing the issue? 

    I

  • Hi Qingjun,

    Customer only enable one EPWM6 INT ISR, we check the CPU IER, PIE IER also PIE IFR register. We found that the 12.7 FPU overflow interrupt is set when the EPWM6 INT ISR work abnormally. 

    This is EPWM6 INT ISR work abnormally, the Register shows below:

    1. CPU IER Register. → Group 3 Interrupt is enabled.



    2. PIE IER Register.


    3. MCAN Register. You can check McanSSRegs.MCANSSIRS and McanSSRegs.MCANSSIECS is set, do you think that it is right for MCAN?



    4. When an EPWM6 INT interrupt is triggered by Zero event, the CPU is about to enter the stack. How can we check whether the CPU is set up correctly at this time? It was suspected that the CPU was executing a low-priority interrupt and could not respond to the high-priority interrupt request of EPWM6 INT. By checking the IER and PIE.IER registers, the code also checked that only the EPWM6 INT/3.6 interrupt was enabled. you can check the point#1 and point#2.
    5. Do you have any others debug dir/suggestion here? Due to customer comment out the below MCAN code, EPWM6 INT/3.6 interrupt can work normally. So do you think it is possible that the CPU is running abnormally and the interrupt cannot be set normally?
  • Hi Qingjun,

    Yes, the EPWM6 Zero event happen, but the EPWM6 INT ISR work abnormally. The EPWM6 INT is 80K. 

  • Hi,

    What does sCanRxPutQue() function do? 

    Did you get the correct MCAN message in the while() loop? 

  • Just noticed that only INT3 (PWM) CPU interrupt is enabled (IE=0x4). 

    Can you share your code that reproduced the same issue? 

  • Hi QJ,

    I have sent the code to you by emali.

  • Yes, we can share the reproduced the same issue here when we received the code from customer's side.

  • Ok, Thanks

  • The root cause of the issue is the RPT instruction generated by compiler. Disabling the RPT generation in CCS project property resolves the issue.

    The interrupt latency (PWM rising edge to GPIO rising edge) without RPT is 320ns (38 CPU clock cycles).