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TIDM-DC-DC-BUCK: Sampling Frequency

Andres Gomez
Intellectual 450 points

Part Number: TIDM-DC-DC-BUCK

Tool/software:

Hi.

I am studying how to use a real-time controller using the F280049C evaluation board and the TIDM-DC-DC-BUCK. I have one question (this is more for information for future designs). I assume that the buck_main.c project has a sampling frequency of 1 kHz since TASKA is running at that frequency. My question is: how do you choose that sampling time (Tsample)? I assume that a higher sampling frequency is better, but it places a burden on the MCU as it demands more computational resources. However, a low sampling frequency may affect the controller's performance and introduce aliasing effects.

  • +1
    TI__Mastermind 20671 points

    Hi Andres,

    TASKA, TASKB, and TASKC are CPU Timers which run at various different frequencies but these are mainly allocated towards background tasks. For control, you should be looking at the ISR frequency (aka the control loop frequency). Your assumptions about the impact of the control loop frequency are correct.

    Which version of the TIDM-DC-DC-BUCK project are you using? We have a powerSUITE-enabled project which makes use of a GUI for easily changing parameters in the project. You can view the ISR frequency in this GUI. The ISR frequency can be changed relative to the switching frequency to be a factor of 1, 2, or 3. You can experiment with a profiling GPIO to see how much time the ISR takes and if there is additional MCU bandwidth to increase the ISR frequency. Usually you can start with the same ISR frequency as your switching frequency when evaluating and adjust from there.

    Regards

    Peter