This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F23885 PLL Input Frequency Question

Other Parts Discussed in Thread: TMS320C28345

The data sheet for the 23885 has a somewhat non clear statement with respect to the PLL and the input frequency from XCLKIN.

 

Reading into the datasheet further it appears that based on the PLL clock multiplier settings, the limit of 30Mhz is imposed in table 6-7.

However, paragraph 3.6.1.2 states to pick an input frequency and division to prevent the VCOCLK to be less than 300Mhz.

There is no way to set the VCOCLK speed to be higher if you cannot set the XCLKIN greater than 30Mhz because the highest PLL mulitplier (PLLCR[]) is 10 (Table 3-16).

So as I read the data sheet the maximum input to the XCLKIN seems to be 150Mhz - (table 6-4), applied to the same input signal would limit the PLLCR to a mulitplier of 2.

Am I reading this right and Table 6-7 should state 30Mhz as the highest input frequency IF the PLLCR multiplier if 10?

We have implemented an input of 40Mhz, with a mulitplier of 7, resulting in 280Mhz (under the 300 specified by paragraph 3.6.1.2) 

We have not seen any issues to date, but we are curious if there is an unseen issue here.

Thanks,


David 

  • You may use input frequencies at the XCLKIN between 4 and 150 MHz (table 6-6) when using an external oscillator. But if you use the PLL, the clock cycle time must be between 33.3 and 200 ns (table 6-7). That's the same as 5 MHz to 30 MHz. Between these two frequencies TI guarantees the correct function of the PLL. If you use 40 MHz input frequency it might work too. And in most cases it will work. But there is no guarantee (e.g. consider whole temperature range) because the chip will operate outside its specifications.

    Best regards,
    Edwin Krasser

  • Thank you for your response. I still have a couple of questions for someone.

    According to the hardware Design Guidelines (spraas1b) a faster input clock can be handled:

    3.1 Clocking Circuit

    The F28x devices offer two options for clock generation: using an onboard crystal oscillator or feeding the external clock to the XCLKIN pin. The frequency of this basic input clock, using an internal oscillator, is in the range of 20 MHz – 35 MHz. The on-chip phase-locked loop (PLL) can be set to multiply the input clock to provide a wide variety of system clock frequencies. Each time you write to the PLLCR register to configure the PLL multiplier, the PLL will take 131,072 cycles to lock. While the PLL is in the process of locking, the device frequency may experience a large swing at the start and end of the locking process. These two potentially abrupt frequency transitions may cause power rail fluctuations. Careful design of the power-supply is needed in order to prevent these transitions from impacting the device operation. Once the PLLCR register is written to, it is recommended that a tight loop be executed until the PLL relocks to the new frequency. Once the PLLCR is written to, writing to the PLLCR again, even with the same multiplier will cause these frequency swings and potential power supply swings. The frequency of the external clock fed to the CLKIN pin can be as high as the maximum frequency at which the CPU can operate (SYSCLKOUT). The CPU can operate within the wider range of that frequency. Further clock signals for all the peripherals are derived from the CPU clock.

    In general, the highest possible frequency for the clock signal is selected to achieve maximum execution speed. However, the other aspect is power consumption because it increases linearly with the CPU clock frequency.

    With this in mind, every reference for the input clock signal simply states the VCOCLK signal must be less than 300 MHz. (sprs439i and others)

    3.6.1.2 PLL-Based Clock Module

    The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 OSCCLK cycles. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) does not exceed 300 MHz.

    If the input (XCLKIN) cannot be set to greater than 30 MHz - then you can never exceed the 300 MHz limit on VCOCLK as stated in several support specs. I am just trying to understand if the limit set in the table 6-7 is a mistake, coincidence or a hold over from an older processor. Making the above paragraph the more accurate statement. 

    Is the PLL really at risk at an XCLKIN of 40MHz? Why? is it temperature, power consumption, or is it something else?

    I want to understand why the limit and not just assume the XCLKIN PLL Enabled table (6-7) in sprs439i is the final word. If it is, I will have to accept that, but would love to have someone confirm why 30MHz is specified.

    This would not be a big a deal if we could find good oscillators at 30 Mhz cheap and within our thermal specs. But 20 and 40 are the ones we are finding.

    P.S Other chips close to the 23885 family state a larger XCLKIN in is allowed - so why the limit on this chip? TMS320F281x - (4 to 150MHz), TMS320C28345 (2 to 150MHz), in fact the 28345 specifically wants a higher than 400MHz signal from the VCOCLK line.

    Thank you for your time,

    Confused :-(


    David

  • Hello!

    Just a short answer: It's interesting that the datasheet tells something different as the hardware design guidelines. But the major question is: Does it work? And if it works it is ok :-).

    Best regards,
    Edwin Krasser

  • David,

    As you have found there are multiple specifications that must be considered when you are setting up your clocking.

    1. If you wish to use the PLL, then you must use XCLKIN <= 30 MHz.
    2. If you are not enabling the PLL then you may use a crystal <= 35 MHz.
    3. If you are not enabling the PLL then you may supply an external clock <= 150 MHz (i.e. up to full CPU speed).

    It's very difficult to tell you what will happen if you are not following the spec.  In general you will see PLLs vary over process (e.g. device to device differences), temperature, and voltage.  If you're running out of spec the PLL might not lock or may eventually lose its lock.

    Brad

  • Brad, thank you for the response. What I want to understand is the discrepancy in the specs. We have successfully run overnight with a scope and saw no loss of lock. Other DSPs allow a much faster input to the PLL. What/why the limitation on this one? Or is the table 6-7 in error and the words in 3.6.1.2 correct?

    Just trying to understand.

    It appears to be working fine, what am I missing here? Is there a temperature limitation? Is there data showing a faster clock will lose lock after a given amount of time? What is the limiting portion of the PLL circuit?

    Thanks,

    David

  • David Clark said:
    What I want to understand is the discrepancy in the specs. We have successfully run overnight with a scope and saw no loss of lock. Other DSPs allow a much faster input to the PLL. What/why the limitation on this one? Or is the table 6-7 in error and the words in 3.6.1.2 correct?

    Please be more specific about the contradiction.  I do not see any contradictions, but rather multiple requirements that you must honor.  In addition to what I already mentioned you must also make sure VCOCLK <= 300 MHz.  The other specs I gave are with regard to the PLL input and this spec is with regard to the PLL output.

     

    David Clark said:

    It appears to be working fine, what am I missing here? Is there a temperature limitation? Is there data showing a faster clock will lose lock after a given amount of time? What is the limiting portion of the PLL circuit?

    If you follow the data sheet requirments we guarantee all parts to work over the specified temperature and voltage range.  If you go outside that spec we cannot make any guarantees.

    If you dump a few gallons of lemon juice into your gas tank I'm sure it will fail.  If you put a drop of lemon juice into your gas tank it would probably be ok (even though that isn't recommended).  Your car manufacturer will not (can not) tell you precisely how much lemon juice you can put into your gas tank before it fails.  They will just tell you not to put lemon juice in your gas tank.

  • Thank you Brad. Lemon juice is good for the soul :-)

    Is there any chance the Data sheet is wrong? A copy paste from some other chip. The TMS320F281x specifies an input range for the PLL to be the same as the input range for XCLKIN. And the TMS320C2834x allows almost all of the range of the XCLKIN.

    I found several data sheets with both the full range allowed (281x and 2834x family) and a shortened range of 5-30MHz for the 2833x and 280x families.

    The lemon juice, it stings my eyes...

  • FYI, I'm trying to find some more info as to why f2833x is different with regard to pll input frequency than some of the other 28x devices. I might not actually find anything which is why I wanted to set some expectations with the lemon juice!  :)

  • Thanks, it all good. I would just like to understand why. Again, everything seems to be working fine.

  • Brad, any progress on getting a reason for the XCLKIN frequency?

  • Sorry, no, I haven't gotten any further info.  I don't expect to hear anything more at this point.