The data sheet for the 23885 has a somewhat non clear statement with respect to the PLL and the input frequency from XCLKIN.
Reading into the datasheet further it appears that based on the PLL clock multiplier settings, the limit of 30Mhz is imposed in table 6-7.
However, paragraph 3.6.1.2 states to pick an input frequency and division to prevent the VCOCLK to be less than 300Mhz.
There is no way to set the VCOCLK speed to be higher if you cannot set the XCLKIN greater than 30Mhz because the highest PLL mulitplier (PLLCR[]) is 10 (Table 3-16).
So as I read the data sheet the maximum input to the XCLKIN seems to be 150Mhz - (table 6-4), applied to the same input signal would limit the PLLCR to a mulitplier of 2.
Am I reading this right and Table 6-7 should state 30Mhz as the highest input frequency IF the PLLCR multiplier if 10?
We have implemented an input of 40Mhz, with a mulitplier of 7, resulting in 280Mhz (under the 300 specified by paragraph 3.6.1.2)
We have not seen any issues to date, but we are curious if there is an unseen issue here.
Thanks,
David