TMS320F28377S: Inquire about setting dead band of epwm under condition of trip zone interrupt

Hi Junyeong,

Can you provide some waveforms to illustrate the behavior you're seeing? 

Can you take a look at the following application report? https://www.ti.com/lit/an/spradf4/spradf4.pdf

We have an implementation that uses the CLB to maintain synchronized EPWM duty all in hardware without the need to handle through software interrupts. Maybe this is similar to what you are implementing?

Regards,

Peter

Hi Peter, 

The picture at the bottom is the waveform of complementary operation with 50% epwm2, 4 duty output and deadband set in a situation where no trip zone interrupt occurs. We can handle dead time using DBRED, DBFED register. 

The picture at the bottom is the waveform of a complementary operation in which a trip zone interrupt occurs when the cmpss input waveform exceeds a certain reference value (DACHVALS.bit.DACVAL and DACLVALS.bit.DACVAL) and outputs an epwm synchronized to the input waveform that exceeds the reference value. In this situation, we set the deadband, but the waveform is output of epwm without the deadband.

It is similar to what you are trying to implement in implementing deadband logic in the linked material, but after checking the data sheet, it seems that it cannot be used because the 377S does not support the CLB function.

Sincerely,
Junyeong Oh

Hi Junyeong,

Thank you for the additional images describing your issue, I misread your part no. but yes its true that CLB is not available to be used on your device. I believe this issue may be related to the configuration of your EPWM peripheral. Is your EPWM statically configured or are you making alterations to the EPWM configuration in your control loop? It would help if you can also send the portion of your code which configures the EPWM module.

I recommend to refer to the SysConfig tool for the initial peripheral configuration. You can access this tool through the dev.ti.com tool chain. You are able to configure the EPWM peripheral through the graphic interface. Then you can see the generated code through the board.h file and compare this to your code to see if there are anything which may be misconfigured.

Regards,

Peter

Hi Peter,

The code at the bottom is the EPWM2 control code, which is configured statically in the main loop and partially controls the epwm from interrupts.

Main loop

PieVectTable.EPWM2_TZ_INT = &EPWM2_TZ_ISR;

EALLOW;
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0x4;
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0x4;
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 2; // DCAH = high, DCAL = don't care
EPwm2Regs.TZDCSEL.bit.DCBEVT1 = 2; // DCBH = high, DCBL = don't care
EPwm2Regs.TZSEL.bit.DCAEVT1 = 1;
EPwm2Regs.TZSEL.bit.DCBEVT1 = 1;
EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;
EPwm2Regs.TZCTL.bit.DCBEVT1 = TZ_NO_CHANGE;
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = 0; // Source is DCAEVT2 Signal
EPwm2Regs.DCBCTL.bit.EVT1SRCSEL = 0; // Source is DCBEVT2 Signal
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = 1; // Source is Asynchronous Signal
EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 1; // Source is Asynchronous Signal
EDIS;

EALLOW;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_HI;

// EPWM Mode Setting
EPwm2Regs.TBPRD = PWM_PRD; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.CMPA.bit.CMPA = PWM_PRD/2;
EPwm2Regs.CMPB.bit.CMPB = PWM_PRD/2;

// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and douwn
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM2A on event A, down count
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM2B on event B, up count
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM2B on event B, down count

//Setup Deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = 0x3;
EPwm2Regs.DBCTL.bit.POLSEL = 0x2;
EPwm2Regs.DBCTL.bit.IN_MODE = 0x0;
EPwm2Regs.DBCTL.bit.OUTSWAP = 0x0;
EPwm2Regs.DBCTL.bit.DEDB_MODE = 0x0;
EPwm2Regs.DBRED.all = 100;
EPwm2Regs.DBFED.all = 100;
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO; // equal to zero or period (TBCTR = 0 or TBCTR = TBPRD)
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm2Regs.TZEINT.bit.DCAEVT1 = 1;
EPwm2Regs.TZEINT.bit.DCBEVT1 = 1;
EDIS;

EALLOW;
EPwmXbarRegs.TRIP5MUX0TO15CFG.all = 0x0000;
EPwmXbarRegs.TRIP5MUX16TO31CFG.all = 0x0000;
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX2 = 1;
EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX2 = 1;
EPwmXbarRegs.TRIPOUTINV.bit.TRIP5 = 0;
EDIS;

Interrupt

interrupt void EPWM2_TZ_ISR(void)
{
EALLOW;
EPwm2Regs.TBCTR = 0;
EPwm2Regs.TZCLR.all = 0x7f;
EDIS;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

}

interrupt void EPWM2_ISR(void)
{
EPwm2Regs.TZFLG.all = 0x00;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

In my opinion, trip zone interrupts, which are often used for OCP(Over Current Protection) and OVP(Over Voltage Protection) purposes, must be activated immediately, so I am asking whether a deadband cannot be provided structurally.

Thanks for your comment.

Sincerely,
Junyeong Oh

Hi Junyeong,

Deadband and CMPSS trip are supported together for the purposes of implementing peak current mode control, see below diagram.

I think you should also configure the cycle by cycle option on the trip zone selection since this will automatically clear the trip on the end of the PWM cycle and re-enable it for the next cycle.

EPwm2Regs.TZSEL.bit.CBC1 = 1;

This is the standard PWM configuration for our reference design's PCMC implementations so this should also be working for you

On a side note, I also noticed that you have set both clock dividers to /1. Can you verify your EPWMCLKDIV register? It should be set to the following since the EPWM clock has a max of 100 MHz on this device.

ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1;


Regards,
Peter

Hi Peter,

It is set to one shot trip, but I have tried various ways to set it to cycle by cycle, including setting it to DCAEVT2 and DCBEVT2, including the code you provided, but it doesn't seem to work to set the deadband.

And when the EPWMCLKDIV register is set to 0, epwm of the desired frequency is generated and 0 seems to be correct.

Sincerely,
Junyeong Oh

Hi Junyeong,

If you have EPWMCLKDIV set to 0, and TBCTL.bit.HSPCLKDIV and TBCTL.bit.CLKDIV set to TB_DIV1, then your EPWM clock will be set to 200 MHz which violates the maximum clock frequency for the EPWM module. Can you try setting the EPWMCLKDIV to 1. You will need to readjust the math that calculates your desired frequency by accounting for the reduced clock from 200 MHz to 100 MHz.

Regards,

Peter

Hi Peter,

As you said, I set EPWMCLKDIV to 1 and reduced TBPRD by half to create the desired frequency. The waveform came out well, but the deadband was still not created. 

I made epwm2a,b complementary by setting TZCTL.bit.TZA and TZB to 2 and 1 respectively, but since the default values ​​are reversed like this, could it be considered that a deadband cannot be provided?

Or, in a trip zone situation, when creating an epwm synchronized to the values ​​of the DACHVAL and DACLVAL registers, is it not possible to change the deadband from the register values?

Sincerely,
Junyeong Oh

Hi Junyeong,

Since it seems the clock is not the reason for the missed deadband, I think the likely solution is to try to use the CBC trip mode in the EPWM as opposed to the one shot trip. This will help to avoid you needing to use an interrupt to clear the trip and as well should allow you to have deadband when the CMPSS trip is detected. Allow me to align with a PWM expert to review your implementation

Regards,

Peter

Hi Junyeong,

Have you been able to verify resolution of your EPWM problem?

Regards,

Peter

Hi Peter,

I haven't solved it yet.

Sincerely,
Junyeong Oh

Hi Junyeong,

You may be able to reference this thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1005096/tms320f28384s-one-question-of-epwm-trip-zone-submodule

Since the TZ comes after DB module (in order to minimize shut-off time for OCP/OVP purposes) this is the intended behavior. So the approach mentioned in the other thread should work. Or also you could configure the CMPSS input to come into the EPWM as a DC event and then configure that event through the Action Qualifier as a T1/T2 event. In these cases the functionality of T1/T2 would match the same as if you used static CMPx value to change the PWM output

Regards,

Peter