TIEVM-VIENNARECT: Build 3: Output Voltage Oscillation Issue

Hi Vigesh,

1. Can you confirm if you have run the hardware at specified conditions in design guide. This helps us eliminate any hardware issues

2. Is the build 2 waveforms looks good?

looks like controller is missing out as the VOUT decreases continuously. Please test at specified load to confirm hardware is good.

Best Regards,

Uttam

Hi Uttam,

Thanks for your reply!

I have confirmed the Hardware is working good by running Build 2 configuration and I have attached Build 2 Input R phase current vs switch node Vs Output Voltage waveform for your reference.

Kindly provide your suggestions for the above problem.

Regards,

Vignesh.

Hi Vignesh, 

VOUT looks good to me. I observe some discrepency on current:

1. C1(input current) during low input voltage, you should see a rectified current signal as shown below. please double confirm across R, Y and B phase as well, if its correctly rectified or not?

2. Is the current(yellow) after adjusting its reference in build 2 is sinusoidal or not? 

2. I assume you are using TIDM1000 hardware, Can you perform the build 2 and build 3 at similar test conditions pointed on design guide and compare the waveforms? If you are using the custom hardware i would recommend checking on the current waveforms as pointed in 1. 

Best Regards,

Uttam

Hi Uttam,

Thanks for your reply!

1. The R, Y, and B rectified currents look similar, and the rectification is working well. I have validated the rectification with an input of up to 115V AC.

2. I have changed the current reference in Build 2, and it is working well and appears sinusoidal. I have validated the Build 2 configuration with current reference of 0.21 at input voltage of 90Vac for 2kW.

3. I cannot perform a similar test as mentioned in Build 3 because, according to the design guide (TIDM1000), the Vout reference is 600V, which is close to my MOSFET's breakdown voltage therefore I have set reference voltage as 380V. For Build 2, I have provided the details above.

I have attached the Build 2 waveform for 2kW for your reference.

I am looking forward to your reply regarding the issue of voltage oscillation in Build 3.

Regards,
Vignesh

For build 3, Can you also look for what is the reference current generated from outer voltage loop. 

If the above value makes sense by running the build 2 with specfied reference current and what is the PWM_dutyPU in A and B region observed? 

2. Also, what is the voltage loop freq.  & current loop freq?

3. If above looks good, 

what is the change done from A --> B as A region waveforms looks good. Can run the SFRA to confirm if the control is doing good here. 

Best Regards,

Uttam

Hi Vignesh,

1. Have you got a chance to observe the voltage loop output? This will provide clear information on root cause for oscillation.

2. If you have done some prior simulation of your system, can you check if the system is stable at the above test conditions?

Best Regards,

Uttam

Hi Uttam,

Thank you for your reply!

1. Have you had a chance to observe the voltage loop output? This could provide clear insights into the root cause of the oscillation.

Unfortunately, when I tried to connect the debugger during switching, it kept disconnecting despite having an isolator in front of the emulator. As a result, I couldn't monitor the voltage loop output. I also attempted to add a ferrite bead, but the CCS debugger window still wouldn't connect during switching.

2. Do you have any prior simulations of your system? If so, could you verify if the system is stable under the test conditions mentioned above?

I currently don't have any simulations for my system. If TI has a simulation file for the Vienna Rectifier, could you please provide it? This would greatly help me debug the issue.

For the previous question:

• Region A: The module operates as a rectifier.
• Region B: The module starts switching.

My voltage loop frequency is 10 kHz, and my current loop frequency is 200 kHz (my switching frequency).

I cannot use SFRA because, as I mentioned earlier, the debugger disconnects during switching.

I suspect saturation might be causing the voltage loop oscillation. This is because a saturation block is added for voltage error in Build 3.

Could you please share your opinion on the above problem as soon as possible? Additionally, if TI has any relevant simulation files, I would greatly appreciate it if you could share them for debugging purposes.

Regards,
Vignesh.

Hi Vignesh, 

1. Can you run from RAM instead of FLASH. Just to see any advantage. Few steps to check for debugger disconnects: https://www.ti.com/lit/an/spracf0c/spracf0c.pdf?ts=1736447945218&ref_url=https%253A%252F%252Fwww.google.com%252F

2. Unfortunately, there is no simulation file for this TI design.

3. I agree on the saturation maybe you are running at wrong Vbus try changing to a different value to see any imporvement. 

Unfortunately, without simulations or calculations its diffiult to identify the error. Atleast, i guess you might have the component calculation sheet while designing your custom board. Please make sure if those made sense. 

Let me know if you need any further help related to TIDM1000 firmware or design.  

Best Regards,

Uttam