TMS320F28377S: IEC60730SWPACKAGES: STL_HWBIST_runMicroTest()

Tool/software:

IEC60730SWPACKAGES: STL_HWBIST_runMicro()

I would like to ask about the HWBIST function.
I am using the example program provided by TI to check the CPU in Micom Self Test.

However, when executing the STL_HWBIST_runMicro function, an NMI occurs and the main loop and interrupts stop.

Since Watchdog is disabled, the reboot does not occur repeatedly.

I want to know the cause of the NMI and how to solve it.
The related documentation is not detailed. I want to know how to use it.

Also, I am using the example program as is and I did not change the initial setting function.
I wonder if I need to change the initial setting.

* Please explain what the register setting values ​​of the function below mean for each line.

void STL_HWBIST_init(const STL_HWBIST_Coverage coverage)
{
EALLOW;

//
// Soft reset the HWBIST controller to put it into a known state.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR5) = 0x80000000UL;

//
// Clear the HWBIST soft reset bit.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR5) = 0x0000UL;

//
// Load target coverage metric.
// DID_01_11
//
/*LDRA_INSPECTED 93 S MR:R.10.1,R.10.3,R.10.4,R.10.5,R.11.1 "LDRA Tool
Issue, both sides of the operation are the same (uint32_t)*/
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR6) = (uint32_t)coverage;

//
// Restart HWBIST.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR5) = 0x000AUL;

//
// DID_01_12
//
if(coverage == STL_HWBIST_95_LOS)
{
//
// Load a 46 cycle count micro run.
// DID_01_10
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR1) = 46UL;

//
// Run launch-on-shift at clock divide of 1.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR7) = 0x0013UL;

//
// Support load for this test.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR8) = 0x0032UL;
HWREG(HWBIST_BASE + HWBIST_O_CSTCSADDR) = 0x4E340000UL;
}

//
// DID_01_12
//
else
{
//
// Load a 61 cycle count micro run.
// DID_01_10
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR1) = 61UL;

//
// Run stuck-at-test at clock divide of 1.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR7) = 0x00010F13UL;

//
// Support load for this test.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCGCR8) = 0x0032UL;
HWREG(HWBIST_BASE + HWBIST_O_CSTCSADDR) = 0x4F4C4272UL;
}

//
// Set pattern count.
// DID_01_13
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCPCNT) = 0x012C06A4UL;

//
// Configuration is done.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCCONFIG) = 0x0005UL;

//
// Set return address.
//
HWREG(HWBIST_BASE + HWBIST_O_CSTCRET) = 0x0000UL;

EDIS;
}