Tool/software:
Dear Sir/Madam,
We are using this 3 phase SPLL to get the frequency. We found the setting time requires more than 10 grid cycles(200ms in a 50Hz grid). The settling time is a concern for me. Do you have any idea?
We are using the procedure as suggested by the SDK document:
SPLL_3ph_DDSRF_init(AC_FREQ_HZ,
(float32_t)(1.0 / ISR1_FREQUENCY_HZ),
(float32_t)(0.00188141f),
(float32_t)(-0.99623717f),
&spll_3ph_1);
Our simulation sampling frequency is 6.4kHz.
The b0, b1 are used exactly as above. We also try different values as per "Software Phase Locked Loop Design Using C2000
Microcontrollers *.pdf"
for example,
const float32_t k_K1 = 0.004885f;
const float32_t k_K2 = -0.99023f;
const float32_t k_3PH_LPF_B0 = 266.6772959f;
const float32_t k_3PH_LPF_B1 = -266.656037f;
const float32_t k_K2 = -0.99023f;
const float32_t k_3PH_LPF_B0 = 266.6772959f;
const float32_t k_3PH_LPF_B1 = -266.656037f;
Thanks