Other Parts Discussed in Thread: C2000WARE
Tool/software:
Hello,
I have been working with multiple boards to establish EtherCAT communication. In the process, I encountered the need to utilize Flash and proceeded accordingly.
However, an issue arose during this process. While there were no interruptions in IPC communication when running on RAM, I noticed that IPC communication fails when running on Flash. Specifically, the IPC communication failure means that the send function within the IPC_write function stops functioning.
As a result, the program gets stuck inside the IPC_write function, and all operations come to a halt.
For Flash implementation, I simply configured the settings by navigating to Properties >> General >> Configuration >> Flash [Active].
Once this setup is complete, the Flash-related functions in the code automatically become active.
For context, my code is based on the EtherCAT example files, "f2838x_cm_echoback_solution" and "f2838x_cpu1_allocate_ecat_to_cm". Below is the Flash implementation and the cmd file used for Flash configuration.
void CM_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef _FLASH
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
//
// Claim the Flash Pump Semaphore before initializing Flash
//
Flash_claimPumpSemaphore(FLASH_CM_WRAPPER);
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
//
// Set Flash Bank and Pump power mode to Active
//
Flash_setBankPowerMode(FLASH0CTRL_BASE, FLASH_BANK, FLASH_BANK_PWR_ACTIVE);
Flash_setPumpPowerMode(FLASH0CTRL_BASE, FLASH_PUMP_PWR_ACTIVE);
//
// Release the Flash Pump Semaphore after initialization
//
Flash_releasePumpSemaphore();
#endif
//
// Turn on all peripherals
//
CM_enableAllPeripherals();
//
// Sets the NVIC vector table offset address.
//
#ifdef _FLASH
Interrupt_setVectorTableOffset((uint32_t)vectorTableFlash);
#else
Interrupt_setVectorTableOffset((uint32_t)vectorTableRAM);
#endif
}MEMORY
{
/* Flash sectors */
CMBANK0_RESETISR : origin = 0x00200000, length = 0x00000008 /* Boot to Flash Entry Point */
CMBANK0_SECTOR0_1_2 : origin = 0x00200008, length = 0x0000BFF7
/* CMBANK0_SECTOR1 : origin = 0x00204000, length = 0x00004000 */
/* CMBANK0_SECTOR2 : origin = 0x00208000, length = 0x00004000 */
CMBANK0_SECTOR3 : origin = 0x0020C000, length = 0x00004000
CMBANK0_SECTOR4 : origin = 0x00210000, length = 0x00010000
CMBANK0_SECTOR5 : origin = 0x00220000, length = 0x00010000
CMBANK0_SECTOR6 : origin = 0x00230000, length = 0x00010000
CMBANK0_SECTOR7 : origin = 0x00240000, length = 0x00010000
CMBANK0_SECTOR8 : origin = 0x00250000, length = 0x00010000
CMBANK0_SECTOR9 : origin = 0x00260000, length = 0x00010000
CMBANK0_SECTOR10 : origin = 0x00270000, length = 0x00004000
CMBANK0_SECTOR11 : origin = 0x00274000, length = 0x00004000
CMBANK0_SECTOR12 : origin = 0x00278000, length = 0x00004000
CMBANK0_SECTOR13 : origin = 0x0027C000, length = 0x00004000
C1RAM : origin = 0x1FFFC000, length = 0x00001FFF
C0RAM : origin = 0x1FFFE000, length = 0x00001FFF
BOOT_RSVD : origin = 0x20000000, length = 0x00000800 /* Part of S0, BOOT rom will use this for stack */
S0RAM : origin = 0x20000800, length = 0x000037FF
S1RAM : origin = 0x20004000, length = 0x00003FFF
S2RAM : origin = 0x20008000, length = 0x00003FFF
S3RAM : origin = 0x2000C000, length = 0x00003FFF
E0RAM : origin = 0x20010000, length = 0x00003FFF
CPU1TOCMMSGRAM0 : origin = 0x20080000, length = 0x00000400
CPU1TOCMMSGRAM0_ECAT : origin = 0x20080400, length = 0x00000400
CPU1TOCMMSGRAM1 : origin = 0x20080800, length = 0x00000800
CMTOCPU1MSGRAM0 : origin = 0x20082000, length = 0x00000400
CMTOCPU1MSGRAM0_ECAT : origin = 0x20082400, length = 0x00000400
CMTOCPU1MSGRAM1 : origin = 0x20082800, length = 0x00000800
CPU2TOCMMSGRAM0 : origin = 0x20084000, length = 0x00000800
CPU2TOCMMSGRAM1 : origin = 0x20084800, length = 0x00000800
CMTOCPU2MSGRAM0 : origin = 0x20086000, length = 0x00000800
CMTOCPU2MSGRAM1 : origin = 0x20086800, length = 0x00000800
}
SECTIONS
{
.resetisr : > CMBANK0_RESETISR
.vftable : > CMBANK0_SECTOR0_1_2, ALIGN(8) /* Application placed vector table in Flash*/
.vtable : > S0RAM /* Application placed vector table in RAM*/
.text : >> CMBANK0_SECTOR0_1_2 | CMBANK0_SECTOR3
.cinit : > CMBANK0_SECTOR0_1_2
.pinit : > CMBANK0_SECTOR0_1_2
.switch : > CMBANK0_SECTOR0_1_2
.sysmem : > C1RAM
.stack : > C1RAM
.ebss : > C1RAM
.econst : > CMBANK0_SECTOR0_1_2
.esysmem : > C1RAM
.data : > C1RAM
.bss : > C1RAM
.const : > CMBANK0_SECTOR0_1_2
MSGRAM_CM_TO_CPU1 : > CMTOCPU1MSGRAM0, type=NOINIT
MSGRAM_CM_TO_CPU1_ECAT : > CMTOCPU1MSGRAM0_ECAT, type=NOINIT
MSGRAM_CM_TO_CPU2 : > CMTOCPU2MSGRAM0, type=NOINIT
MSGRAM_CPU1_TO_CM : > CPU1TOCMMSGRAM0, type=NOINIT
MSGRAM_CPU1_TO_CM_ECAT : > CPU1TOCMMSGRAM0_ECAT, type=NOINIT
MSGRAM_CPU2_TO_CM : > CPU2TOCMMSGRAM0, type=NOINIT
.TI.ramfunc : {} LOAD = CMBANK0_SECTOR0_1_2 | CMBANK0_SECTOR3,
RUN = S0RAM | S1RAM | S2RAM,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
< Flash code of f2838x_cm_echoback_solution > < 2838x_FLASH_lnk_ecat_cm.cmd >
MEMORY
{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B0, length = 0x000250
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD0 : origin = 0x00C000, length = 0x000800
RAMD1 : origin = 0x00C800, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00D000, length = 0x001000
RAMGS1 : origin = 0x00E000, length = 0x001000
RAMGS2 : origin = 0x00F000, length = 0x001000
RAMGS3 : origin = 0x010000, length = 0x001000
RAMGS4 : origin = 0x011000, length = 0x001000
RAMGS5 : origin = 0x012000, length = 0x001000
RAMGS6 : origin = 0x013000, length = 0x001000
RAMGS7 : origin = 0x014000, length = 0x001000
RAMGS8 : origin = 0x015000, length = 0x001000
RAMGS9 : origin = 0x016000, length = 0x001000
RAMGS10 : origin = 0x017000, length = 0x001000
RAMGS11 : origin = 0x018000, length = 0x001000
RAMGS12 : origin = 0x019000, length = 0x001000
RAMGS13 : origin = 0x01A000, length = 0x001000
RAMGS14 : origin = 0x01B000, length = 0x001000
RAMGS15 : origin = 0x01C000, length = 0x001000
/* Flash sectors */
FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CPUTOCMRAM : origin = 0x039000, length = 0x000800
CMTOCPURAM : origin = 0x038000, length = 0x000800
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
codestart : > BEGIN, ALIGN(4)
.text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(4)
.cinit : > FLASH1 | FLASH2 | FLASH3, ALIGN(4)
.switch : > FLASH1, ALIGN(4)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMGS0
#if defined(__TI_EABI__)
.init_array : > FLASH1, ALIGN(4)
.bss : > RAMLS4 | RAMLS5
.bss:output : > RAMLS3
.bss:cio : > RAMLS5
.data : > RAMLS5
.sysmem : > RAMLS5
/* Initalized sections go in Flash */
.const : > FLASH5, ALIGN(4)
#else
.pinit : > FLASH1, ALIGN(4)
.ebss : > RAMLS5
.esysmem : > RAMLS5
.cio : > RAMLS5
/* Initalized sections go in Flash */
.econst : >> FLASH4 | FLASH5, ALIGN(4)
#endif
ramgs0 : > RAMGS0, type=NOINIT
ramgs1 : > RAMGS1, type=NOINIT
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT
MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT
/* The following section definition are for SDFM examples */
Filter_RegsFile : > RAMGS0
Filter1_RegsFile : > RAMGS1, fill=0x1111
Filter2_RegsFile : > RAMGS2, fill=0x2222
Filter3_RegsFile : > RAMGS3, fill=0x3333
Filter4_RegsFile : > RAMGS4, fill=0x4444
Difference_RegsFile : >RAMGS5, fill=0x3333
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(4)
#else
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(4)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
void main(void)
{
HW_Init();
MainInit();
bRunApplication = TRUE;
do
{
IPC_Write(IPC_CM_L_CPU1_R, IPC_FLAG2, IPC_CMD_READ_MEM1, 6);
MainLoop();
DEVICE_DELAY_US((uint32_t)(2.));
BackTicker++;
} while (bRunApplication == TRUE);
HW_Release();
}
< 2838x_FLASH_lnk_ecat_cpu1.cmd > < IPC code of f2838x_cm_echoback_solution >
Could the issue be a conflict between Flash and IPC, or is it simply a problem with my code implementation?
Best regards.
