TMS320F28388D: IPC usage like CLA MSG RAM ?

Adrien Thurin

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Hi,

I have so many problems with implementing IPC, it's been a massive issue. I took me a while to get something running, and a recent change in the data structures shared between CPUs has broken it again, and I don't have the faintest idea what went wrong. I have spent so much time on these issues, time I am not spending on the actual operation of the microcontroller ... it is extremely frustrating.

Is there a way to make things easier ? For instance to have a software implementation that would resemble the CPU CLA MSG RAM, to write and read data asynchronously, without all the hassle of the interrupts, flags and such ?

Thanks in advance,

Best regards,

Adrien

over 1 year ago

0 Ozino Odharo over 1 year ago

TI__Mastermind 21600 points

HI Adrien,

Sorry to hear about your difficulties. Can you clarify if you're using the CLA in your application or just the IPC?

I would recommend starting with a blank IPC example,https://dev.ti.com/tirex/explore/node?node=A__APCOgL6qulEhjoVekLevtA__C2000WARE__1kRFgrO__LATEST&placeholder=true

As for the CLA MSG RAM Example, I would recommend looking into the CLA Workshop https://www.ti.com/video/series/control-law-accelerator--cla--hands-on-workshop.html

Please note this video breaks down when to use the MSG RAM.

Regards,

Ozino

0 Adrien Thurin over 1 year ago in reply to Ozino Odharo

Intellectual 556 points

Hi Ozino,

I use both CLA and both cores for this project.

CLA is easy. One R/W section that is only R for the other, and vice versa. Data transfer is easy.

IPC is ... not. I am transferring 3 data packets, the code is virtually the same, and yet 1 out of 3 doesn't work for no apparent reason. And it already took me weeks to get there, starting from the examples provided.

So the question is ... is it possible to make the IPC easier ? transform IPC into something that would resemble the CLA / CPU communication ?

For instance, this might be a very bad idea, but what if I filled the CPU1TOCPU2RAM with 1 big table, and put the CPU1 data somewhere I choose in this table. Would CPU2 be able to read this table whenever it chooses to do so, without going through the IPC interrupt mechanism ?

I understand that, since the code for both cores is compiled and linked independently, it is not possible to make the location of one variable built in one program known to the other. Which explains the interrupt mechanism, that sends the address of the data to be transferred to the receiving core. However, if there is a way to force the address of the variables in the CPU1TOCPU2RAM, then the CPU2 could just go and get the data whenever it needs to, thus making the transfer much easier (and similar-ish to the data transfer between CPU and CLA).

Thanks in advance,

Best regards,

Adrien

0 Adrien Thurin over 1 year ago in reply to Adrien Thurin

Intellectual 556 points

Hi Ozino,

By browsing in the "similar topics", I found my answer, based on the following posts :

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/994087/tms320f28377d-cpu2-to-cpu1-ipc-msg-ram-access

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1092074/tms320f28377d-cpu1-not-receiving-update-of-shared-arrays-whereas-cpu2-can/4044296#4044296

https://software-dl.ti.com/ccs/esd/documents/sdto_cgt_methods_to_force_an_ordering_of_global_variables.html

In a shared .h file, I put the memory addresses of the variables I want to exchange :

#define CPU1_TO_CPU2_BASE_ADDRESS			0x03A000
#define CPU1_TO_CPU2_STATUS_ADDRESS			(CPU1_TO_CPU2_BASE_ADDRESS)
#define CPU1_TO_CPU2_MEASUREMENTS_ADDRESS	(CPU1_TO_CPU2_STATUS_ADDRESS + sizeof(status_t))

#define CPU2_TO_CPU1_BASE_ADDRESS			0x03B000
#define CPU2_TO_CPU1_STATUS_ADDRESS			(CPU2_TO_CPU1_BASE_ADDRESS)
#define CPU2_TO_CPU1_MEASUREMENTS_ADDRESS	(CPU2_TO_CPU1_STATUS_ADDRESS + sizeof(status_t))

And then in each program, the variables with the same name and location :

#pragma LOCATION(s_status_cpu1_to_cpu2, CPU1_TO_CPU2_STATUS_ADDRESS)
static status_t s_status_cpu1_to_cpu2	

#pragma LOCATION(s_status_cpu2_to_cpu1, CPU2_TO_CPU1_STATUS_ADDRESS)
static status_t s_status_cpu2_to_cpu1	

#pragma LOCATION(s_measurements_cpu1_to_cpu2, CPU1_TO_CPU2_MEASUREMENTS_ADDRESS)
static measurements_t s_measurements_cpu1_to_cpu2;

#pragma LOCATION(s_measurements_cpu2_to_cpu1, CPU2_TO_CPU1_MEASUREMENTS_ADDRESS)
static measurements_t s_measurements_cpu2_to_cpu1;

And now both CPUs can read the data coming from the other CPU asynchrounsly, without going through the interrupt process.

This seems to work for CPU1 and CPU2 because the memory maps of both cores are identical. It is easy to identify where the data written by one core can be read by the other core.

However, the memory mapping with the CM is fairly different.

CPU1 memory :

   CPUTOCMRAM      : origin = 0x039000, length = 0x000800
   CMTOCPURAM      : origin = 0x038000, length = 0x000800

CM memory :

CPU1TOCMMSGRAM0  : origin = 0x20080000, length = 0x00000800
CMTOCPU1MSGRAM0  : origin = 0x20082000, length = 0x00000800

Therefore, if CPU1 writes data in CPUTOCMRAM (for instance at base address 0x039000), I don't know where I can read it from the CM. And vice versa.

What is the correspondance between the memory sections of the CM and of CPU1 ? Is CPU1's 0x039000 equal to CM's 0x20080000 ?

Thanks in advance,

Best regards,

Adrien

0 Ozino Odharo over 1 year ago in reply to Adrien Thurin

TI__Mastermind 21600 points

Hi Adrien,

Glad to hear you made progress in your development. Thank you for the feedback.

Regarding the memory sharing between the CM and CPU, I would recommend taking a look at the CM examples provided in C2000Ware.

It will show where you can read the CM memory

https://dev.ti.com/tirex/explore/node?node=A__ANwwURrRiqh4Fp5sl6q1qQ__C2000WARE__1kRFgrO__LATEST

Regards,

Ozino

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TMS320F28388D: IPC usage like CLA MSG RAM ?