Tool/software:
Good morning. Just started the project development for new device.
The customer design requirements for bootloader and communications are as follows:
- On factory release the board should be loaded with firmware using single serial interface, both CPU1 and CM firmwares. Using of JTAG is not permitted.
- During normal functional operation board should communicate with host using the same single serial interface.
- For firmware update the custom software bootloader should be implemented on CM core, allowing to update firmware of CPU1 and CM cores.
First I see the default SCIA (GPIOs 29,28) port can be selected for SCI Boot mode on unprogrammed device with DIP switch. Then, if application on CPU1 detects the CM FLASH is unprogrammed, it starts custom bootloader to load firmware to CM core First question here is how to access CM's FLASH sectors from CPU1?.
Then both cores are programmed, CPU1 application configures crossbar to map UART port from CM core to same GPIO pins 29, 28. Thus, CM core will use this port to communicate with host.
Then firmware update is needed, CM application starts custom software bootloader. Ang again, the question is how CM core can access CPU1's FLASH sectors?
