TMS320F28386S: Creating field bootloader

Hello,

I recommend you refer to the Serial Flash Programming Application Note for your development, this document details how to update CPU1 and the CM cores with a flash kernel. Although the SCI flash kernel executes in the RAM, it can be modified to run from the flash. The SCI flash kernel example code can be found here:

• C2000Ware_5_04_00_00\driverlib\f2838x\examples\c28x_dual\flash_kernel

I see. The question is how to start up flash kernel during series production without JTAG?

Hi,

Are you asking how to update a device without using JTAG?

What is the current boot configuration of the device? Have you programmed the OTP or are you using the default boot modes?

Please see this user's guide for more details regarding C2000 bootloading: https://www.ti.com/lit/ug/sprujh3/sprujh3.pdf

Best,

Matt

To be exact: The production facility receives boards with unprogrammed MCU placed in. There are DIP switches on board, one of them is controlling the boot pins to set the boot mode to SCI boot. Then, the engineer at the production facility have to connect the board to serial interface and run some application to program both CPU1 and CM flash image via this interface.

Thank you, that's clear.

I suppose, if I connect UART_RX and SCIA_RX pins together, then the application code on CPU1 starts up, it will map UART_TX pin to the GPIO29 with XBAR, and let CM core to handle the communication protocol on the same serial interface. After that, when firmware update is needed, I wil have 2 options, 1st, I can branch to flash kernel in RAM  on CPU1 and CM to update firmware, or, if application hangs, use DIP switch to fallback to stock booloader on SCIA on powerup. Correct?

Hi,

For the SCI flash kernel example, CPU1 keeps control of the SCI peripheral and sends the data over IPC when requested by CM's kernel functions. In other words, you can use SCI to program the flash with a CM application.

"CPU1 keeps control of the SCI peripheral and sends over the data CM needs for its kernel functions when requested by CM. The CM kernel can signal the CPU1 kernel that it needs a certain function executed, for example sciaGetWordData. CPU1 will get the result of executing the function and place it into Message RAM for CM to copy over and use for any of its commands."

Please refer to Section 5.2.2 CPU1-CM Kernels for specific details on how CPU1-CM interact to download the CM kernel and application.

Best,

Matt

Yes, it is clear. But during normal operation, not during firmware update, I need CM to control this serial port to implement the communications protocol.

Hi,

Yes, this is feasible. Note that the UART TX/RX can be routed to the GPIO42/43 or GPIO84/85 pins (see datasheet for routing).

Please refer to the examples in C2000Ware to see how this configuration is done (C2000Ware_5_04_00_00\driverlib\f2838x\examples\cm\uart)

Best,

Matt

Yes, but I need it to be the same pins as default SCA port, which is 29 and 28, because I need to be bootloader and normal communications on the same port. This is why I plan to connect SCA RX and UART RX together, and use CROSSBAR to map UART TX to the GPIO29.