• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 83 subscribers
  • Views 251 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIDM-DC-DC-BUCK: LAUNCHXL-F280049C

Mike Allette
Intellectual 355 points

Part Number: TIDM-DC-DC-BUCK

Tool/software:

Hi,

I'm trying to understand the timing of the  TIDM-DC-DC-BUCK reference design in order to implement this on a design that I'm working on.

Do you know if it’s possible to bring out signals related to the ADC timing to probe? Or something in code composer console that can display counters for the timing? I added a GPIO to go hi and low when going in and out of the ISR. Also, I tried to add a GPIO to go high when the ADC is triggered for SOC but couldn’t find a good place in the code to see when the ADC starts converting and ends converting. I also attached my edited version of the code adding the GPIOs.

buck_F28004x.zip

I made a rough timing diagram of how I understand the loop is supposed to operate based on what I read in the code. I have the ADC being triggered by the ePWM, then the ADC starts its conversion. Between ADC SOC (sample & hold, and conversion to digital) and EOC, I’m estimating about 280ns of latency, based on the MCU datasheet and the ACQPS, before the ADC interrupt is triggered to start the Buck ISR. The Buck ISR latency is from what I measure with the GPIO. Does any of this seem off to you?

However, when I probe the ISR, there looks to be about 3.62us of delay from the ePWM. Also, I looked at the startup of the project once I hit resume un code composer and noticed that the Buck_ISR starts running on its own before the ePWM starts switching. Which may be why the ISR and the ePWM look off sync. This confused me because I was under the impression that the ISR was dependent on the ADC trigger, which is dependent on the ePWM. Do you have any insight on why this is happening? Is this supposed to happen?

Buck Start Up

 

Buck Start Up Zoomed In

 

Respectfully,

Mike Allette

  • 0
    TI__Expert 4660 points

    Mike,

    Time taken by ADC can not be profiled by code. It is specified in datasheet and device trm.

    For ePWM not syncing with ISR profiling GPIO:

    Please see the following function and its definition by ctrl+click the function. This decides when your interrupt should start. In this code its at the end of acquisition window and not at the end of the conversion as you suggested. This is done to improve overall control loop latency by starting interrupt little ahead so that time required to enter ISR, context save and ADC reading can be run parallel while ADC taking conversion time. Profiling GPIO toggling time is may be factored in this one.

    If you want this interrupt to happen in sequential manner, you can do that by changing the define on line147 in "buck_user_setting.h" 

    Line 147 --> #define BUCK_VOUT_ADC_INT_MODE        ADC_PULSE_END_OF_CONV 

             

    Also for profiling, you can only profile code portion of ISR, total latency will include ADC conversion time + computation + ePWM update time.

    Regards,

    Sumit

  • 0 in reply to Sumit Patil1
    Intellectual 355 points

    Hi Sumit,

    Good to chat with you again. Thank you for your response. Thank you for that ctrl+click shortcut, that was very helpful.

    So are these two settings for ADC_setInterruptPulseMode(), "ADC_PULSE_END_OF_ACQ_WIN and ADC_PULSE_END_OF_CONV", the Early Interrupt Mode and Late Interrupt Mode that the datasheet talks about?

     

    For ADC_PULSE_END_OF_ACQ_WIN setting, is there a default number of clock cycles that gets added at the end of the acquisition window if the ADC_setInterruptCycleOffset() finction is not configured? I didn't see a configuration for that in this project.

    Also, I changed the pulse mode to ADC_PULSE_END_OF_CONV and was still getting the same output that I was getting before with the ADC_PULSE_END_OF_ACQ_WIN setting. I also still see the 3us delay between the EPWM and the ISR. It looks like the ISR starts before the ePWM starts switching. Is that supposed to happen? Isn't the ISR dependent on the ADC interrupt flag? Is the ADC interrupt engaging before the ePWM starts?

  • 0 in reply to Mike Allette
    TI__Expert 4660 points

    Mike,

    Its just the way you look at it. It is happening sequentially. 

     

    There are bunch of stuff that are deciding triggering ISR as shown below.

    In this example CMPB event is triggering ADCSOC and ADC-C is triggering ISR as shown below. ADC EOC happens when all channels on ADC-C are done converting that includes all the signals on ADC-C. This time is additional to ACQPS and ADC conversion timing before GPIO in your ISR sets.

    You can refer 13.7 EOC and Interrupt Operation section of device TRM for elaborated explanation regarding these interrupt flow. 

    Let me know if that makes sense.

    Regards,

    Sumit