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Setup to PWM trigger ADC in 28335

Kuldeep Kumar Mynampati
Intellectual 320 points

Hi,


Hi all,

I have set up my ADC in cascaded and Simultaneous mode and to trigger both Sequencers when the PWM (TBCTR == TBPRD). Below is the setup
in ADC init code snippet.

Question: Once my ADC is triggered by EPWM1 on reaching the TBCTR == TBPRD. Do, I need to clear the EPWM interrupt?


// EPWM-1 are set for SOC in SEQ1.
   AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1   = 1;     // Enable EVASOC to start SEQ1
   AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1   = 1;  // Enable SEQ1 interrupt (every EOS)
  
// AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2   = 1;     // Enable EVASOC to start SEQ2.
// AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2     = 1;     // Enable SEQ2 interrupt (Every EOS).
 
// Start ADC with EPWM1 (TBCTR == TBPRD) event:
   EPwm1Regs.ETSEL.bit.SOCAEN    = 1;     // Enable SOC on A group
   EPwm1Regs.ETSEL.bit.SOCASEL                  = 2;     // NEW, trigger ADC at TBPRD
   EPwm1Regs.ETPS.bit.SOCAPRD    = 1;     // Generate pulse on 1st event

Regards,
Kuldeep

 

  • 0
    TI__Guru 64470 points

    It is not necessary to handle the EPWM interrupt for the ADC Start-Of-Conversion (SOCx) event.  The description of that functionality is provided in the EPWM user's guide (SPRUG04) in Section 2.8.1.  Figure 45 illustrates the logic diagram.

    If you are simultaneously interrupting the CPU from the EPWM event, then yes, you would need to handle the event flags and PIE events in order to rearm the interrupt mechanism.

     

  • 0 in reply to BrandonAzbell
    Intellectual 360 points

    Hello,

    I have been trying to setup up my adc to be triggered by epwm, exactly the same way the author of this thread is doing, but I do not get any result when I change voltage on any pin.

    Here are some code-snippets:

    PWM-setup:

       EPwm1Regs.ETSEL.bit.INTSEL =
   ET_CTR_ZERO;     // Select INT on Zero event
   EPwm1Regs.ETSEL.bit.INTEN =1;               // Enable INT
   EPwm1Regs.ETPS.bit.INTPRD =ET_1ST;           // Generate INT on 1st event
   EPwm1Regs.ETSEL.bit.SOCAEN =1;        // Enable SOC on Agroup
   EPwm1Regs.ETSEL.bit.SOCASEL =1;//4;   // modified
   EPwm1Regs.ETPS.bit.SOCAPRD =1;        // Generate pulse on 1st event

    ADC-setup:

    AdcRegs.ADCTRL3.bit.ADCCLKPS =2;
AdcRegs.ADCTRL1.bit.CPS =1;
AdcRegs.ADCTRL1.bit.ACQ_PS =4;
AdcRegs.ADCTRL3.bit.SMODE_SEL =0x1;
AdcRegs.ADCMAXCONV.all = 0x0033; // 4 double conv's each sequencer (8 total)AdcRegs.ADCTRL1.bit.CONT_RUN =0; // manual reset
AdcRegs.ADCCHSELSEQ1.bit.CONV00 =0x0;
//(…) conv 1 to 10...
AdcRegs.ADCCHSELSEQ3.bit.CONV11 =0x7;

    The interrupt service routine works just fine, the pie-groups are acknowledged on every interrupt as shown in the examples.

    When I call the sequence like this in every ISR

    Value1=AdcRegs.ADCRESULT0;//trying to read
//(…)
Value2=AdcRegs.ADCRESULT4;//trying to read

    There is no change of value 1 or 2 in the watch window. As you see, I don't care for the right shift of these bits at this time, I will correct that later on. I know that the adc works, as it does in the in the adcsoc-example, so the problem is - as usual - sitting right in front of the screen in my case :-)

    Can anybody help me out here?

    Looking forward to your answer.

    Regards,

    E_