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F29H850TU: WDT on Core 2 /Core 2 of F29H850TU multicore system

Mrinali Lothey
Prodigy 100 points
Part Number: F29H850TU


Tool/software:

Creating a new questions as response on my original question did not solve my query.

My question is specifically wrt Watchdog timer implementation on Core 2 or Core 3 of a multicore system and the issue discussed  in this thread.

Does implementing WDT in a multicore system require additional code to ensure that a system reset on Core 2 / Core 3 will restart execution from main? 

If I want to perform a system reset when WDT Times out in Core 2 or Core 3, will need to utilize ESM or IPC to communicate with  CPU1 to perform a system reset?
  • 0
    TI__Genius 14625 points

    Hi,

    Yes if CPU2 or CPU3 WDRSn occurs, then the error events in ESM.

    CPU2RSn,CPU3RSn, CPU2WD and CPU3WD are captured as error events in ESM.

    CPU2WD/CPU3WD causes respective core reset. ESM error events are captured when core reset occurs that can be used to create XRSn from ESM itself.

    Thanks