Tool/software:
Hello!
I’m working with the F29x family and configuring ECC error handling using EAM and ESM as described in TI’s SDAA104 application note.
I understand that all high-priority errors (HPERR), including ECC errors, are aggregated and signaled via ESM, typically triggering an NMI ISR?
My question:
How can my NMI ISR reliably determine if the HPERR was caused by an ECC error (single or double bit) versus another high-priority error source (e.g., illegal instruction)?
What I’ve found so far:
- The EAM error type registers log a specific value for each error source.
- For ECC errors, the error type value is
0x40
for uncorrectable (double-bit, high priority) and0x80
for correctable (single-bit, low priority). - Other HPERRs have different error type values (see Table 4-1 in SDAA104).
Is the recommended approach to read the EAM error type register in the ISR and match against these values?
If so, is there a best practice for accessing these registers and handling multiple error sources in the same ISR?
Any code examples or clarification on robust error source identification in the ISR would be appreciated!