Hello,
I have a customer who is considering the DP83822HRHBT PHY Interface for one of their upcomming designs, and as a result is referencing the TMDSCNCD28388D's circuitry in their considerations. Regarding the TMDSCNCD28388D's circuitry, as well as ethernet clocks in general, they have the following questions:
Q1: What is the purpose of using a 25MHz clock for the PHY and the MCU?
→My assumptions are the following:
-
- Using a 25MHz clock allows for the use of MII, RMII (PHY master mode), and REVMII, flexibility is ideal for an EVM.
- A single 25MHz oscillator is used to eliminate PPM error for industrial applications, but for general applications multiple oscillators/crystals can be used.
Q2: What is the recommended way to implement the clock signals for RMII between the DP83822HRHBT and TMDSCNCD28388D?
→My current thoughts are:
-
- For PHY master mode: Connect a 25MHz oscillator to the PHY's XI pin, and connect the RX_D3 pin to the MCUs RMII_CLK to provide the 50MHz clock to the MCU.
- For PHY slave mode: Connect a 50MHz oscillator via a clock buffer (or two seperate 50MHz oscillators without a buffer) to the PHY's X1 pin as well as the MCUs RMII_CLK. (Instead of an external clock for the MCU is it fine to use PLL to multiply a 25MHz MCU clock to 50MHz, or is the/an other method recommended?)
Please let me know if you need any more information.
Thank you,
Michael
