JTAG with F28M35H52C1

Paul Buschmeyer

Other Parts Discussed in Thread: ISO7220C, ISO7220A

We have developed a hardware design using the F28M35H52C1 processor. We are having a problem with the JTAG interface (a BIG problem, we can't load a program...). We used the Concerto DIMM100 Control Card design (1 Feb 2012) as a reference design for the JTAG interface. We have successfuly programmed the FT2232H EEPROM, e.g. Code Composer Studio 5.2 recoginizes the emulator when we plug in the USB cable. However, when we test the connection, we cannot connect. We've run the dbgjtag utility from Code Composer Studio and what we find is that our design has a different DR and IR path length than if we run the test using the Concerto DIMM100 Control Card.

Here are the results from the Control Card dbgjtag

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

C:\Users\BUSCHM~1\AppData\Local\.TI\2620625255\ 0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product. This utility will load the adapter 'jioserdesusb.dll'. The library build date was 'May 30 2012'. The library build time was '22:52:27'. The library package version is '5.0.747.0'. The library component version is '35.34.40.0'. The controller does not use a programmable FPGA. The controller has a version number of '4' (0x00000004). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal. The controller is the FTDI FT2232 with USB interface. The link from controller to target is direct (without cable). The software is configured for FTDI FT2232 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded. The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded. The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words. This test will be applied just once.

Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words. This test will be applied just once.

The JTAG DR Integrity scan-test has succeeded.

[End]

Here is the result from our interface.

[Start]