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Piccolo 2803x ADC 1st sample issue - NONOVERLAP in sequential mode?

Wolfgang R.
Intellectual 386 points

Hello,

Using F28033, ADC clocked at 60MHz

Errata Sheet SPRZ295K: "For simultaneous sample mode, discard the first sample of both the A and B channels at the beginning of every series of conversions."

This is what we are doing right now, and it works.

ADC User Manual SPRUGE5F Figure 37. Timing Example for NONOVERLAP Mode: "The NONOVERLAP bit in the ADCCTL2 register, when enabled, removes the overlap of sampling and conversion stages. This will eliminate 1st sample issue and improve INL/DNL performance."

Q1: Is NONOVERLAP also effective in simultaneous sampling mode? I.e., with NONOVERLAP=1, is the simultaneous sampling of A+B delayed until previous conversion of B is complete?

Q2: If answer(Q1)=yes: Does this solve the 1st sample issue and eliminate the need for discarding the 1st pair of results?

Main reason why we'd like to do this ist to get the actual sampling of the 1st sample nearer to the SOC (PWM center). Discarding effectively means 26 CLKs additional delay, which is a lot with 100kHz PWM at small duty cycles. Reduced throughput with NONOVERLAP would be no problem, but we'd like to have the 1st pair of samples as close to PWM center as possible.

  • 0
    TI__Guru 60865 points

    Q1:  Simultaneous sampling will still work in non-overlap mode and the two samples will still be captured at the same time.  

    Q2: Yes, this will fix the first sample issue in simultaneous mode as well.

    The tradoff in timing is essentially this:

    For 60MHz, overlap, the samples are roughly available after:

    7(S+H A dummy and S+H B dummy) + 13(conv. A dummy) + 13(conv. B dummy) + 0 (S+H A and S+H B, this is 0 cycles because S+H latency is hidden by pipelining, it would not be 0 ) + 13(conv . A) + 13(conv. B) = 59 cycles (60MHz)

    For 30MHz, non-overlap, the samples are roughly available after:

    7(S+H A and S+H B) + 13(conv. A) + 13(conv. B) = 31 cycles (30MHz) = 62 cycles (60MHz)

    So samples are actually ready sooner if discarding the first sample, but if using the workaround then the S+H for the first two signals will be closer to the trigger.  

  • 0 in reply to Devin Cottier
    TI__Guru 60865 points

    EDIT:  "it would not be 0"...if the converter were in non-overlap mode

  • 0 in reply to Devin Cottier
    Intellectual 386 points

    Ok.

    So we can run the ADC at 60MHz, simultaneous sampling, NONOVERLAP=1, and do not have to discard the 1st pair of samples, gaining S+H of these closer to SOC trigger - at the cost of slower throughput and marginally increased latency.

    Great! Thanks for the quick response. Question fully answered :-)

  • 0 in reply to Wolfgang R.
    TI__Guru 60865 points

    Actually not quite.  If you want to avoid the first sample, you need to do both non-overlap mode and use 30MHz ADCCLK.  Note the timings from my previous post use 30MHz for the situation where the first sample is not discarded. 

  • 0 in reply to Devin Cottier
    Intellectual 386 points

    Ok. having asked for 60Mhz operation I misinterpreted "= 62 cycles (60MHz)": the 60 MHz are CPU clocks, not ADC clocks, quite obvious at a 2nd look.

    So the answer to Q2 is "No. You can't work around the 1st sample issue running the ADC at 60MHz with NONOVERLAP=1". At 60MHz, the 1st sample issue is always present, whether using NONOVERLAP or not.

    The abovementioned note in SPRUGE5F "The NONOVERLAP bit in the ADCCTL2 register, when enabled, ... will eliminate 1st sample issue ...." is only valid for 30MHz ADC clock, not for 60 (that little note was the cause for this question).

    Correct?

  • 0 in reply to Wolfgang R.
    TI__Guru 60865 points

    You are correct.  The "62 (60MHz)" was trying to show the time for the 30MHz non-overlap workaround case in the same units as the discarded sample case.  It would have been clearer if I had just converted both to ns.  

    To summarize:

    First Sample Issue? ADCCLK = 60MHz ADCCLK = 30MHz
    Overlap Yes Reduced
    Non-overlap Reduced Completely Fixed