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Custom F28027F board - JTAG

Other Parts Discussed in Thread: DRV8301, ISO7220M

Hi everyone,

I'm working on a custom ESC based on the F28027F and DRV8301 gate driver. I have no experience breaking out JTAG, so I was hoping someone with some experience could take a glance at the schematic attached and tell me if I'm going to run into any trouble.

*Have I broken out everything I need to - to the JTAG header?

*I am running the board off of a single battery with the 3.3v coming from the internal buck (DRV8301). Does the ISO7220M somehow create an 'isolated' 3.3V supply or should I short pins 1 and  8 on the ICs?

*What is a good XDS100V2 emulator ~$100 for this? I was looking at this but it says the core architecture is MSP430 - I think is completely different and incompatible with C2000? I can't seem to find much low cost for C2000 although i'm pretty sure it should exist?

Thanks for any help/ advice

  • Patrick,

    Based on your description, this is not a very high-voltage board.  Because of this you probably don't really need isolation between your MCU and the JTAG header.  This means that the ISO72xxx chips (and C48) are not needed.  Once done 3V3-EXT-ISO would connect directly to +3.3V, etc.  However, if you want to be safe and have the isolation you'll need to power the JTAG side via an isolated DC/DC.  Something like the below:

    R52 looks to be unnecessary & potentially problematic as it will override anything done on JP2.  I'd remove it.

    I must admit that VDD1 and VDD2 seem like they're not connected up right.

    From a brief look everything else looks decent.

    Hopefully, this helps.

    Thank you,

  • Patrick,

    The emulator you linked to is the lowest cost, and the one I use if isolation isn't required.  It's a bit cheaper on our TI eStore but currently Out of Stock apparently.


  • Thanks Chris,

    I actually found the one on Farnell after I saw the estore was out of stock... then decided that it wasn't suitable because the 'core architecture' is listed as MSP430.

    *Are XDS100 emulators architecture independent? - Could I use that emulator on both MSP430s and C2000s?

  • the emulator will work on any of the TI MCUs.  Each "family" typically has a different header pin-out though. There are 10, 14, 20 pin as standard, and some of the new ARM versions I think just have a few.  There are always adapters....

    anyways, that emulator works well for Piccolo for the price.


  • Thanks-  exchanging money for goods now/

  • Thanks Brett,

    I'll go ahead and drop the isolation, R52 & C48. The board will be run on about 16V but allow up to 24V.

    Brett Larimore said:
    I must admit that VDD1 and VDD2 seem like they're not connected up right.

    Is this because they are tied to mismatched pins on the MCU? -I grabbed the symbol and footprint from Farnell but it must have been from an earlier revision because the (VDD and 1 or 2 others, all the GPIOs etc are correct) pins do not match the current numbering, they are correct as per the data sheet though. *or is there another reason?


  • Patrick,

    VDD1 and VDD2:
    My main concern is that I don't see how they are being generated.  In your first image, I don't see how they connect to 3.3 or GND, etc.  Also note that in your schematic, VDD2 connects up to VSS on the MCU (danger!). 

    Thank you,

  • Thanks Brett,

    Just read my last post and realised that it probably didn't make much sense to anyone but me.

    "VDD2 connects up to VSS on the MCU (danger!)."

    VDD2 is actually pin 43 on the F28027F, this is what I meant by 'not matching current numbering'... I have gone through and methodically checked numbering and remapped pins where necessary, should have done this in the first place, so it should be easier to follow now.
    *Just to make absolutely certain, the F28027 and F28027F are physically identical and have the same pin outs?

    Re VDD1&2, I guess they are effectively DC floating which I thought was fine? Datasheet: "CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time." ....

    If you literally meant that you couldn't see where they are connected, on the JTAG page in the top left I have them through 2.2uF caps to ground, C41 and C39.

    Hopefully this revision is closer to being workable?

  • Patrick,

    I believe that what you now have is correct.  Obviously you'll want to do the final checks on your own though.  I think the main problem I had in the last post had to do with the misleading numbering. 

    To answer your questions:
    Just to make absolutely certain, the F28027 and F28027F are physically identical and have the same pin outs?
    [BL] Correct, the F28027F is physically equivalent to the F28027

    VDD1&2, I guess they are effectively DC floating which I thought was fine?
    [BL] Yes, if the internal vreg is used (VREGENZ pulled low on the MCU) VDD1 and VDD2 should float with their own cap.  I recently found out that it is slightly more ideal if VDD1 and VDD2 (your naming) are shorted.  If you wish you can do this, but what you have will also work.

    Thank you,