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Generate 12.5Mbps signal with F28335

Other Parts Discussed in Thread: TMDSDOCK28335, CONTROLSUITE, SN74AHC594

Hello,

I acquired the experimental kit TMDSDOCK28335 and started programming based on "Flashing Leds" program included in the Control Suite. My target with this evaluation board is to generate a 12.5Mbps 14 bit-sequence and in paralell, sample it at 50MHz so as to detect the sequence.

As an attempt to start developing this idea, I tried to generate a square signal with a determinate bit rate using "Flashing Leds" code. To do so, I decreased CPUTimer0 and variable “Gui_LedPrd_ms” and the resulting square signal was the expected at low frequencies but as long as I decreased the CPUTimer0, I noticed that I was not able to generate periods lower than 1usec. I tried to disable B and C tasks of the background loop but it didn't work either. The rest of parameters (such as clock configurated at 150MHz) were the same as in the original "Flashing leds" project.

Can anyone give me some advise?

Thank you so much

  • Laura, did you try PWM or HRPWM peripheral to generate square wave? You might be able to achieve what you're looking for.

    Regards,

    Gautam

  • Dear Gautam,

    Thank you for your answer. No, I didn't try this option..I will try to find out how to generate the sequence using PWM, I am a little bit confused right now.

    Regards,

    Laura

  • Laura said:
    I am a little bit confused right now.

    Why what happened?

    You can check "epwm_up_aq" example project that can be found here:

    C:\ti\controlSUITE\device_support\f2833x\v133\DSP2833x_examples_ccsv4\epwm_up_aq

    Regards,

    Gautam

  • Dear Gautam,

    This is the first design I make with DSP (I always worked with FPGAs) and I am not familiar with all the DSP options and peripherals. So I have to read and understand how to used PWM and apply it to my design.

    Thank you for your support, it is really appreciated.

    Laura

  • So I have to read and understand how to used PWM and apply it to my design.

    Yup, some reading is required. If you face any difficulty while implementing or understand any concept, don't hesitate to drop by.

    Regards,

    Gautam

  • Dear Gautam,

    Thank you for your help. As I explained in my first post, my target is to sample at 50MHz a 14-bit sequence serial input (a kind of UART communication). The generation of a 12.5Mbps sequence is just to simulate the serial input signal and test if the program works.  Do you think it is feasible with this DSP TMS320F282335? 

    Thank you so much

    Best regards,

    Laura

  • Hi Laura,

    I think you might have some difficulty efficiently sampling a 50MHz signal. If you sample the GPIO directly, you will use all of the available CPU bandwidth.  Ideally you would use a communication peripheral like McBSP or SPI, but I am pretty sure these are slower than 50MHz.

    Maybe you could try connecting your bit stream to a shift register (maybe something like SN74AHC594) and then read the shift register output using 8 GPIOs in parallel.  This should reduce the CPU bandwidth requirement by 8x (or more if you daisy chain more shift registers together).  If you aren't using the XINTF for anything else, you could read the data in using this module (ignore the address lines and just use the data lines for a parallel read) otherwise just use 8 consecutive GPIO.  

  • Thank you so much Devin. Your support is really appreciated. I wil reconsider my design according to your information.

    Thank you!

  • Dear Devin,

    I am considering the use of SPI peripheral for receiving the 12.5Mbps signal. However, this input signal is asynchronous. Do you think it is really possible to store this 14-bit 12.5Mbps serial sequence using SPI peripheral if it is set to opperate at 12.5Mbps and without an input clk signal?

    Thank you for your support and sorry for the inconvenience

  • Laura,

    The SPI module won't clock in any data without a SPICLK. The only way that I can think that this would work would be that you would detect the start of the transmission in software, then use the ePWM to generate 12.5MHz clock which you then loop-back to the SPICLK?  I think this would be very difficult to impossible to implement reliably, since you won't have that much flexibility to synchronize the ePWM based clock with the incoming bit stream.

     

  • Devin,

    Thank you so much for your reply, This is what I suspected... and I suppose that trying to do this using McBSP involves the same problem since it also requires a clk. May I conclude that it is not feasible with this DSP?

    thank you once again

  • Hi Laura,

    Yeah, it seems like it would be hard to implement this without some external hardware.  

    Since you are familiar with FPGA/CPLD, is there a way to implement this interface in a small/low cost programmable device, and then connect that to the DSP via one of the supported interfaces?

  • Hi Devin,

    I totally agree that this is the solution. Thank you so much for all your support!

    Best regards

    Laura

  • Laura,

    If you don't mind me asking, what kind of application is this for?  What are you trying to communicate with that has this high-speed communication interface? What is the fastest asynchronous communication interface this type of application would need?

  • Devin,

    It is a control application. I need to read a 12.5Mbps signal and according to the received bit stream, change a external configuration.Due to demanding requirements in the switching speed,a high-speed communication interface is needed.

    Thank you once again for all your support,

    Best regards

    Laura