This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

internal oscillator to GPIO

Other Parts Discussed in Thread: CONTROLSUITE

Hello-

I'm using the 28027 chip, 48 pins.

I'm looking at SPRUFN3C (rev. 10/09), page 44 at the oscillator logic diagram.

Is there a way for me to get from CLKCTL to GPIO Mux?

I want to capture the internal oscillator on GPIO18 (XCLKOUT).

Thanks!

 

  • Okay .. most likely I am missing something obvious ... but is it not possible to connect them externally ? However, remember the capture unit will not be able to capture the device clock frequency .. check the maximum frequency the capture module is design to accomodate.

  • Maybe I am the one missing something obvious!

    I don't know how I would connect externally. The way that I understand it is that the internal oscillator only runs inside the chip.

    Where does the clock signal generated by the internal oscillator come out?

    I had thought to configure registers such that the signal could come out on GPIO18 but wanted verification that this is possible.

    Can you explain which capture module please?

    Thanks!

  • Nora -

    It is possible to bring whichever clock is clocking the system out on the XCLKOUT pin. The XCLKOUT pin is not dependent on INTOSC1, INTOSC2 or EXTOSC. Any of these clocks can be brought out on XCLKOUT depending on whichever one was selected via CLKCTL to clock the device system.

    To bring the system clock (SYSCLK) out on XCLKOUT pin:

    1. SetGPIO mux selection for GPIO18 such that XCLKOUT is selected.:

    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;  // GPIO18 = XCLKOUT

    2. Set XCLKOUT to SYSCLKOUT ratio:

    SysCtrlRegs.XCLK.bit.XCLKOUTDIV=2; // XCLKOUT = SYSCLKOUT

    Note - if your PLLCR is set to 0, and DIVSEL is set to 3 (i.e. /1 mode), and CLKCTL selects INTOSC1 as the clock which sources SYSCLKOUT, then you will have the INTOSC1 frequency come out on XCLKOUT pin.

  • OK thank you!

     I am trying to change these registers using the Memory Window in CCS 3.3.

    However I am getting unpredictable results. When I write over the value in the register, does this force the bits?

    Is there an EALLOW setting I need to change prior to doing this?

    Thanks!

     

  • The System Control User guide for your device should tell you which registers are EALLOW protected when writing to them in code. I am fairly sure all these registers are EALLOW protected.

    Yes, writing to the watch window modifies the bits directly.

    When writing from the watch window, you do not need to allow EALOW protection.

     

  • Hi-

    I am not getting a clock signal on GPIO18, pin24 on 48 pin 28027.

    This is how my registers are set up:

    Address       Name              Bits inside

    0x6F8A         GPADIR          0x0FFF

    0x6F8B         GPADIR          0xFFFF

    0x7012          CLKCTL         0X7E12

    0X7021         PLLCR           0X0000

    And then, 0x7011 PLLSTS reads 0x0181

    So I change bit 3 to a "1" to get 0x0185

    I left GPAMUX and GPACTL registers as all "0's"

    Any thoughts?

    Thanks!

     

  • Nora,

    As mentioned in my previous post, you have to set the GPAMUX register for XCLKOUT output -

    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;  // GPIO18 = XCLKOUT

    That is what is missing.

  • Thank you for the reply.

    I have changed register 0x6F88 to 0x00000030.

    Still no joy.

    I am total NOOB so please suggest other things I should look for...?

    Thanks!

  • Nora -

    My previous post also mentioned that you have to set XCLK to enable XCLKOUT - so the XCLK register must = 2. You are missing the steps to enable XCLKOUT.

    My CLKCTL register = 0x6400.

    To get started, you might want to download and run the 2802x header files and peripheral examples (found in controlSUITE) - the whole process for doing this is in the SysCtrl.c file - and the clock setup is run by every example in the package.

  • yes I have the XCLK set to 0x2, sorry forgot to list it.

    Will check CLKCTL ...

    thanks.