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TMS320C28345 ePWM sync lost on update frequency, run as phase shift full brigde

Hello,

i have a problem with the ePWM modul, it is losing the sync from the master module.

The working frequency is changing between 10kHz and 200kHz. The phase shift has to be changed to the new frequency.
It works better if i do not use the shadow registers but at the frequency change i get one or more jitter.

The inti of the moduls:

EPwm2Regs.TBPRD = (unsigned int)(HighspeedClock/EPwmPUFreq)-1; // Set timer period
	EPwm2Regs.TBPHS.half.TBPHS = 0;       			// Phase is 0
	EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;		// Count up
	EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;			// Disable phase loading
	EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;			// Use Shadow Register
	EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;		// Output Sync Pulse at Zero
	EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;		// Use Shadowed Mode for Compare Register A
	EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;		// Use Shadowed Mode for Compare Register B
	EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;	// Load Compare Register A when Counter is zero
	EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;	// Load Compare Register B when Counter is zero
	EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   		// Clock ratio to SYSCLKOUT
	EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;			// Time-base Clock Prescale
	EPwm2Regs.CMPA.half.CMPA = EPwm2Regs.TBPRD/2;   // Set Compare A value to 50% PWM
	EPwm2Regs.CMPB = EPwm2Regs.TBPRD/2;             // Set Compare B value to 50% PWM
	EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;            	// Set PWM2A on Zero
	EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;          	// Clear PWM2A on event A, up count
	EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET;          	// Set PWM2B on Zero
	EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;   			// Clear PWM2B on event B, up count
	EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     	// Select INT on Zero event
	EPwm2Regs.ETSEL.bit.INTEN = 0;                	// Disable INT
	EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; 	// Enable Dead-band module
	EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; 		// Active Hi complementary B channel is inverted!
	EPwm2Regs.DBFED = 25; 							// FED = 25 TBCLKs to make sure that not both transistors can be enabled at the same time
	EPwm2Regs.DBRED = 25; 							// RED = 25 TBCLKs
	EPwm2Regs.TBCTL.bit.FREE_SOFT = 0;				// stop Timebase at TBCTR=TBPRD on emulator stop
	EPwm2Regs.TZCTL.bit.TZA = 3;					// No action on Trip event
	EPwm2Regs.TZCTL.bit.TZB = 3;					// No action on Trip event
	EPwm2Regs.TBCTR = 0x0000;                  		// Clear counter

	// Setup ePWM 3 - PU-Positive Slave - Variable Phase
	EPwm3Regs.TBPRD = (unsigned int)(HighspeedClock/EPwmPUFreq)-1;	// Set timer period
	EPwm3Regs.TBPHS.half.TBPHS = 0;       			// Phase starts by 0
	EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; 		// Count up
	EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;   		// Enable phase loading
	EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;			// Use Shadow Register
	EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;		// Forwards Sync from Master
	EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   		// Clock ratio to SYSCLKOUT
	EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;			// Time-base Clock Prescale
	EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;		// Use Shadowed Mode for Compare Register A
	EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;		// Use Shadowed Mode for Compare Register B
	EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;	// Load Compare Register A when Counter is zero
	EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;	// Load Compare Register B when Counter is zero
	EPwm3Regs.CMPA.half.CMPA = EPwm3Regs.TBPRD/2;   // Set Compare A value to 50% PWM
	EPwm3Regs.CMPB = EPwm3Regs.TBPRD/2;             // Set Compare B value to 50% PWM
	EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;            	// Set PWM3A on Zero
	EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;          	// Clear PWM3A on event A, up count
	EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;           	// Set PWM3B on Zero
	EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;            // Clear PWM3B on event B, up count
	EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     	// Select INT on Zero event
	EPwm3Regs.ETSEL.bit.INTEN = 0;                	// Disable INT
	EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; 	// Enable Dead-band module
	EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; 		// Active Hi complementary B channel is inverted!
	EPwm3Regs.DBFED = 25; 							// FED = 25 TBCLKs to make sure that not both transistors can be enabled at the same time
	EPwm3Regs.DBRED = 25; 							// RED = 25 TBCLKs
	EPwm3Regs.TBCTL.bit.FREE_SOFT = 0;				// stop Timebase at TBCTR=TBPRD on emulator stop
	EPwm3Regs.TZCTL.bit.TZA = 3;					// No action on Trip event
	EPwm3Regs.TZCTL.bit.TZB = 3;					// No action on Trip event
	EPwm3Regs.TBCTR = 0x0000;                  		// Clear counter

Update of the frequency:

period = (200.0e6 / freq_pos)-1 + 0.5;			// + rounding
			if(period%2 == 0) period--;
			compare = period >> 1;							

			// Master
			EPwm2Regs.TBPRD = period;
			EPwm2Regs.CMPA.half.CMPA = compare;
			EPwm2Regs.CMPB = compare;

			//  Slave
			phase_pos = (65535 / EPwm3Regs.CMPA.half.CMPA) * EPwm3Regs.TBPHS.half.TBPHS;	// Remember Phase
			EPwm3Regs.TBPRD = period;
			EPwm3Regs.CMPA.half.CMPA = compare;
			EPwm3Regs.CMPB = compare;
phase = ((unsigned long)pos * (EPwm3Regs.TBPRD/2)) / 65535;		//phase in clk's
			if (phase < 3) phase = 3;
			if (phase > EPwm3Regs.TBPRD) phase = EPwm3Regs.TBPRD;
			EPwm3Regs.TBPHS.half.TBPHS = phase;
I have here an obvious problem?

With best regards

Christian