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F28044 interrupt time

John Knieriemen
Prodigy 410 points

We are using the TI evaluation module with the F28044 processor.  What is the delay from the time that it receives and INT to the time that it can put out GPIO info?

 

This is the same project that we talked about last week, so the 2us or less time is important.

  • 0
    Mastermind 7585 points

    John,

    the internal latency ( time between the edge of an external interrupt signal and the execution of the first ISR-instruction) is 16 clock cycles. Adding a few cycles (4-8)  for additional context save in an C-based ISR code you can execute the first GPIO instruction after 20-24 CPU clock cylcles, whiich is for a 100 MHz device a delay of 200 - 240 nanoseconds.

    You can actually measure that time: if you use an external interrupt (GPIO) as interrupt source, the edge will clear an internal counter( XINTCNT). This counter is incremented by the CPU clock. If you read this counter in the first instruction in the ISR, you get the number mentioned above.

    Regards