Chip enable line behaviour with fifo interrupts on the 28377D

Oscar,

Currently, there is no way to configure the default behavior of the SPISTE signal. You are seeing the proper behavior of the SPISTE signal. When there is no data in the Transmit buffer, SPISTE will return to it's inactive state. because of this, you have a few options:

1. Configure the SPI transmit interrupt to be some value smaller than the full FIFO depth. Say you configure the interrupt level to be 8 words. On the first interrupt, you will fill the FIFO with 8 words, immediately upon the first word being copied from the FIFO to the shift register, the interrupt will fire again, where you will load the next 8 words. The FIFO will at that point have 15 words. The next time the FIFO drops below 8 words, the interrupt will fire and you will load up the next 8 words, consistently keeping the FIFO running. You can use this strategy with any burst size, as long as the number of words you load into the FIFO does not exceed the maximum depth of the FIFO.

2. Instead of using the default SPISTE signal, use a software controlled GPIO to as the Chip Select. There are a bunch of threads on the forum describing this strategy. The basic gist is that your software will manually control the Chip Select signal. The Software can drive it active at the beginning of the transmission, and inactive once the full transmission is complete.

Strategy 1 will generate more interrupts from the SPI, but your Chip Select will be driven by the SPI as required without any other CPU intervention. Strategy 2 will require some checks in Software to determine when/if the active active transmission is complete and additional writes to the GPIO registers to control your custom Chip Select signal.

Regards,
Mark